An example of how to use the Xilinx ISE toolchain from the command line

This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.

My Lab Assigments from Bachelor Degree, This repo includes the projects for digital systems II Lecture (EEM334)

This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim tools

A Verilog based Fractal Set Generator for the Xilinx Artix 7

Tiny 4-bit CPU using AMD2901 bit slice (https://github.com/Amrnasr/AM2901) and program memory initialized from a file

FPGA Tetris written in Verilog

Digital System Design Project - Spring 2020

The Repository contains the code of various Digital Circuits

Xilinx Virtual Cable (XVC) Server implementation for use with an Arduino UNO/Leonardo

An 8-bit multiplier is synthesized and simulated in Xilinx ISE using Verilog HDL. The multiplication is performed using Vedic Mathematics which is proved to consume less power and faster than conventional multipliers.

Simple system built around VHDL implementation of Am9080 8-bit CPU based on 29XX bit-slice series of devices, as described here: https://en.wikichip.org/w/images/7/76/An_Emulation_of_the_Am9080A.pdf

A single cycle CPU running MIPS instructions on Xilinx FPGA

16-bit MIPS processor implemented in Verilog (as a part of Computer Organisation course)

This project aims to test how fast you can respond after seeing a visual stimulus or rather hand-eye coordination.

ALINX-AX309-RTC-UART-VHDL-FPGA-Xilinx-Spartan6

FPGA Messbauer hardware (generator, emulation of signal from gamma-source registered and amplified

A multiple cycle CPU running MIPS instructions on Xilinx FPGA

RISC based 8-bits five stage pipelined processor, operating at 585 MHz clock frequency with 19 I/O pins and 28 instructions having 5 Addressing formats. Tested on Xilinx Artix-7 FPGA.