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10 public repositories
matching this topic...
Example designs showing different ways to use F4PGA toolchains.
Updated
Mar 27, 2024
Verilog
Caravel is a standard SoC harness with on chip resources to control and read/write operations from a user-dedicated space.
Updated
May 15, 2024
Verilog
VexRiscV system with GDB-Server in Hardware
A toy L4 load balancer running on FPGA
Briey SoC on ECP5 (ICESugar Pro)
Updated
Mar 26, 2022
Verilog
Briey SoC on Sipeed Tang Primer
Updated
Mar 26, 2022
Verilog
A small framework to simplify the creation of custom instruction for the VexRiscv.
Updated
Jan 6, 2022
Scala
Yet another faux-retro game system
Updated
Mar 3, 2024
Verilog
Co-architect 32-bit open-source RISC-V soft-cores for improved FPGA implementations
Updated
Jul 3, 2022
Python
Source files and notes of my Final Year Project, as part of an MEng in Electronics and Information Engineering from Imperial College London
Updated
Jan 19, 2024
Python
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