chipsalliance / verible Star 1.2k Code Issues Pull requests Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server productivity parser formatter analysis style-linter linter language-server-protocol syntax-tree lexer yacc systemverilog hacktoberfest lsp-server systemverilog-parser systemverilog-developer sv-lrm verible Updated May 12, 2024 C++
a2k-hanlon / linter-veriloghdl Star 9 Code Issues Pull requests Atom linter for Verilog/SystemVerilog, using Icarus Verilog, Slang, Verible or Verilator. compiler linter slang verilog systemverilog hdl iverilog icarus verilator verible Updated Jul 12, 2023 CoffeeScript
aGhandhii / systemverilog-auto-lint-format Star 0 Code Issues Pull requests SystemVerilog Automatic Linter and Formatter Using Verible Tools formatter linter verilog shell-script systemverilog powershell-script posix-sh githook posix-shell verible Updated Oct 21, 2023 Shell
stornado / Open-IC-DEV Star 0 Code Issues Pull requests Open IC DEV 是一个基于 iVerilog, SystemC, UVM, verible, verilator, oh-my-zsh,vscode 等开源工具链的开发环境。 docker debian vscode systemverilog systemc uvm system-verilog iverilog verilator verible Updated Jan 7, 2024 Dockerfile