systemverilog
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BDD Gherkin implementation in native SystemVerilog, based on UVM.
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Jun 8, 2024 - SystemVerilog
Veryl: A Modern Hardware Description Language
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Jun 8, 2024 - Rust
Code generation tool for control and status registers
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Jun 7, 2024 - Ruby
SystemVerilog RTL and UVM RAL model generators for RgGen
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Jun 7, 2024 - Ruby
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
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Jun 7, 2024 - C++
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
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Jun 7, 2024 - SystemVerilog
An HDL package manager.
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Jun 7, 2024 - Rust
Examples of SystemC from the High-Level Systems Design course of the Master's Degree in Electronics at the Costa Rica Institute of Technology.
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Jun 7, 2024 - C++
WIP: Very much a RISC-V core, written in SystemVerilog
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Jun 6, 2024 - SystemVerilog
Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator
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Jun 6, 2024 - Python
🇯 JSON encoder and decoder in pure SystemVerilog
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Jun 6, 2024 - SystemVerilog
A truly opensource camera serial interface. No frills. No backdoors that compromise security. Outstanding signal integrity. Hi-rez video pipeline with remote connectivity. For Sony, Series7 & open FPGA makers on limited budget. Augments openXC7 CI/CD, challenging its timing-savvy. Promotes the lesser-known EU boards.
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Jun 6, 2024 - Verilog
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
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Jun 6, 2024 - SystemVerilog
The final product is amazing - a small and simple RISC-V processor that I implemented myself. The assignments are gradual and each stage makes use of the tools I have acquired so far.
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Jun 6, 2024 - SystemVerilog
Functional verification project for the CORE-V family of RISC-V cores.
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Jun 7, 2024 - Assembly
System verilog learning journey. Here in this repo you learn about how to write system verilog test bench using verilator tool
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Jun 6, 2024 - C++
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