risc-v
Unlike most other ISA designs, the RISC-V ISA is provided under open source licenses that do not require fees to use. A number of companies are offering or have announced RISC-V hardware, open source operating systems with RISC-V support are available and the instruction set is supported in several popular software toolchains.
Notable features of the RISC-V ISA include a load–store architecture, bit patterns to simplify the multiplexers in a CPU, IEEE 754 floating-point, a design that is architecturally neutral, and placing most-significant bits at a fixed location to speed sign extension. The instruction set is designed for a wide range of uses. The base instruction set has a fixed length of 32-bit naturally aligned instructions, and the ISA supports variable length extensions where each instruction could be an any number of 16-bit parcels in length. Subsets support small embedded systems, personal computers, supercomputers with vector processors, and warehouse-scale 19 inch rack-mounted parallel computers.
Here are 1,673 public repositories matching this topic...
Parallella RISC-V Prebuilt Images
-
Updated
Aug 18, 2016
A cache simulator, using the C++ language, to simulate a direct-mapped, fully associative and set-associative cache. It has a set of memory reference generators to generate different sequences of references.
-
Updated
May 24, 2017 - C++
Flight software to control a future quadcopter using a Hifive1.
-
Updated
Jun 15, 2017 - C
A program that translates programs written in assembly language into machine code and vice versa.
-
Updated
Jun 20, 2017 - C++
Eclipse Plugin for RISC-V GNU Toolchain
-
Updated
Jun 27, 2017 - Java
-
Updated
Jul 11, 2017 - Go
Magenta kernel port to RISC-V
-
Updated
Jul 17, 2017 - C
Linear algebra accelerators for RISC-V (published in ICCD 17)
-
Updated
Oct 5, 2017