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README.md

README.md

 
 

alu.v

alu.v

 
 

branch.v

branch.v

 
 

controller.v

controller.v

 
 

lsu.v

lsu.v

 
 

memory.v

memory.v

 
 

mux2.v

mux2.v

 
 

mux4.v

mux4.v

 
 

processor.v

processor.v

 
 

regfile.v

regfile.v

 
 

sanity_check.hex

sanity_check.hex

 
 

system.v

system.v

 
 

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risc-v

An easy implementation of RISC-V in Verilog.

Features

  • Implemented only integer arithmetic instructions of RISC-V ISA 2.0.
  • Clean code, fairly simple design with great extensibility.

Status: under development as a personal side project.

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An easy implementation of RISC-V in Verilog.

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risc-v

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