processor-design
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Simulation of Designs of Basic Computer & Processor Architecture(4-bit MIPS CPU, Floating Point Adder) in Logisim as assignments of Computer Architecture Sessional course of CSE 306 of CSE, BUET
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Aug 11, 2018 - VHDL
Computer Architecture: 01:198:211 This course covers the fundamental issues in the design of modern computer systems, including the design and implementation of key hardware components such as the processor, memory, and I/O devices, and the software/hardware interface.
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Sep 18, 2018 - C
Verilog implementation of a subset of MIPS 32 Bit Processor Instructions, ISA design, Assembler Design and Compiler design
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Nov 28, 2018 - Verilog
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Dec 10, 2018 - VHDL
FPGA implementation of a special purpose processor that performs single operation using custom ALU. You can take look at the [related blog post] (https://overengineer.github.io/SpecialPurposeProcessor) for further details.
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Jan 3, 2019 - Verilog
An 8-bit processor in VHDL based on a simple instruction set
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Mar 7, 2019 - VHDL
ARM architecture single-cycle processor designed according to book "Digital design and computer architecture: ARM edition" as a practice in digital design.
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Jun 27, 2019 - SystemVerilog
A simple processor designed using Verilog and Altera DE1 development board.
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Apr 22, 2020 - Verilog
EE577b-Course-Project
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May 6, 2020 - Verilog
A synthesizable pipelined RISC-V processor. (Digital System Design, Spring 2020, NTUEE)
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Jul 20, 2020 - Verilog
The reference design of EE113's final project (Digital integrated Circuit design Fall 2020) at ShanghaiTech University
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Aug 12, 2020
Custom processor implemented in logisim-evolution
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Nov 8, 2020 - Python
Domain Specific Hardware Accelerators - VLSI CAD Project
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Jan 11, 2021 - Bluespec
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Feb 2, 2021 - Verilog
Verilog Implementation of a Z80 Compatible Processor Architecture - Lab Report
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Mar 28, 2021 - TeX
A multi-cycle RISC CPU (processor) like MIPS-CPU architecture in VHDL ( a hardware-side implementation )
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Jun 19, 2021 - VHDL
tinyGPU: A Predicated-SIMD processor implementation in SystemVerilog
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Jul 14, 2021 - SystemVerilog
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