An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support for 3-5 way superscalar execution. The core is pin-to-pin compatible with the RISCY cores from PULP

Multi-Processor System on Chip with RISCV-32 / RISCV-64 / RISCV-128

Multi-Processor System on Chip with OpenRISC-32 / OpenRISC-64

Multi-Processor System on Chip with MSP430-16

Examples of OpenMP for instruction-level parallelism.