A complete open-source design-for-testing (DFT) Solution
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Updated
Mar 26, 2024 - Swift
A complete open-source design-for-testing (DFT) Solution
FAN (fan-out-oriented) ATPG (Automatic Test Pattern Generation) and Fault Simulation command line tool
A prototype of Concolic Testing engine for SystemVerilog, developed as part of PFN summer internship 2018.
Combinational ATPG generator based on D-Algorithm
Logic circuit analysis and optimization
Generate ATPG for fault detection on Verilog circuits. C++/QT
Raspberry Pi 4 is used to drive ATPG stuck-at patterns to an IC. Python is used to drive the patterns and check for expected levels on the scan_out pins (4 chains in this example). A Perl script is used to parse the ATP pattern data into Python lists (I prefer to parse text files using Perl).
Algorithm that extracts a circuit from a netlist and performs fault collapsing
Design of a BIST module for RISC-V fault testing
an implementation of the FAN ATPG algorithm in c++ and verilog.
Fault Simulation | Parallel Fault Simulation | Deductive fault Simulation | Test Coverage
Post-manufacturing test analysis
Simple EDA tool for fault reduction and testing for combinational circuits
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