x86: Fix aliasing issues with SIMD instructions #6524
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Several of the SIMD instructions have incorrect semantics when both the source and destination register are the same. Essentially, parts of the source register are modified via writes to the destination register while they are still needed.
This PR fixes the following:
f30fe6c0 "CVTDQ2PD XMM0, XMM0" with XMM0=0x0000_000a_0000_000a
x86:LE:64:default
(Existing): { RAX=0x41d0090000000000_4024000000000000 }x86:LE:64:default
(This patch): { XMM0=0x4024000000000000_4024000000000000 }0f5ac0 "CVTPS2PD XMM0, XMM0" with XMM0=0x41200000_41200000
x86:LE:64:default
(Existing): { RAX=0x4004800000000000_4024000000000000 }x86:LE:64:default
(This patch): { XMM0=0x4024000000000000_4024000000000000 }660f7cc0 "HADDPD XMM0, XMM0" with XMM0=0x3fd3333333333333_3fd3333333333333
x86:LE:64:default
(Existing): { RAX=0x3feccccccccccccc_3fe3333333333333 }x86:LE:64:default
(This patch): { XMM0=0x3fe3333333333333_3fe3333333333333 }f20f7cc0 "HADDPD XMM0, XMM0" with XMM0=0x3e99999a_3e99999a_3e99999a_3e99999a
x86:LE:64:default
(Existing): { RAX=0x3fc00000_3f99999a_3f19999a_3f19999a }x86:LE:64:default
(This patch): { XMM0=0x3f19999a_3f19999a_3f19999a_3f19999a }660f7dc0 "HSUBPD XMM0, XMM0" with XMM0=0x3fd3333333333333_3fd3333333333333
x86:LE:64:default
(Existing): { RAX=0xbfd3333333333333_0000000000000000 }x86:LE:64:default
(This patch): { XMM0=0 }f20f7dc0 "HSUBPD XMM0, XMM0" with XMM0=0x3e99999a_3e99999a_3e99999a_3e99999a
x86:LE:64:default
(Existing): { RAX=0xbe99999a_00000000_00000000_00000000 }x86:LE:64:default
(This patch): { XMM0=0 }