RISCV: handle divide by 0

[Sleigh-InSPECtor]

As apart of a research project testing the accuracy of the sleigh specifications compared to real hardware, we observed unexpected behaviour in the divide and remainder instructions for RISCV. These include the div, divu, rem, remu, divw, divuw, remw, remuw instructions. According to section 7.2 of the riscv-spec-20191213 specification the result of dividing by zero is all 1's, and the result of the remainder of zero is the dividend. The current behaviour does not check if the divisor is zero which causes a division exception on these cases. Handling this case does add an if statement which shows in decompilation, but is how it is handled in both AARCH64 and ARM with the SDIV and UDIV instructions, and MIPS16 with the div and divu instructions. There is also an edge case for overflowing division which has not been handled.

Decompilation without fix

int division(int param_1,int param_2)
{
  gp = &__global_pointer$;
  return param_1 / param_2;
}

Decompilation with fix

int division(int param_1,int param_2)
{
  gp = &__global_pointer$;
  if (param_2 == 0) {
    param_1 = -1;
  }
  else {
    param_1 = param_1 / param_2;
  }
  return param_1;
}