RISCV: clear lsb in compressed jump instructions

[Sleigh-InSPECtor]

As part of a research project testing the accuracy of the sleigh specifications compared to real hardware, we observed an unexpected behaviour in the c.jalr, c.jr, and ret instructions for RISCV. According to section 16.4 of the 20191213 unprivileged specification, these instructions expand to the jalr instruction. In section 2.5 it says that when calculating the address for jalr the least significant bit is cleared. While the current behaviour leaves this bit as is. Current behaviour for the c.jalr instruction also jumps to the inst_next address instead of the registers value when the ra register is used.