Skip to content
View Merinyeldho's full-sized avatar
🎯
Focusing
🎯
Focusing
Block or Report

Block or report Merinyeldho

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Pinned

  1. Low-Power-and-Area-Efficient-Carry-Select-Adder-CSLA- Low-Power-and-Area-Efficient-Carry-Select-Adder-CSLA- Public

    Verilog implementation modified carry select adder

    Verilog 2

  2. SAP1-computer-verilog SAP1-computer-verilog Public

    Verilog implementation of SAP-1 computer architecture

    Verilog 1

  3. Multilingo-Translator Multilingo-Translator Public

    Translator

    Python