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Bringup gpios on vc707 target #1872

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Bringup gpios on vc707 target #1872

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6 changes: 6 additions & 0 deletions fpga/src/main/scala/vc707/Configs.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,7 @@ import freechips.rocketchip.tile.{XLen}

import sifive.blocks.devices.spi.{PeripherySPIKey, SPIParams}
import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
import sifive.blocks.devices.gpio.{PeripheryGPIOKey, GPIOParams}

import sifive.fpgashells.shell.{DesignKey}
import sifive.fpgashells.shell.xilinx.{VC7074GDDRSize}
Expand All @@ -23,6 +24,7 @@ import chipyard.harness._
class WithDefaultPeripherals extends Config((site, here, up) => {
case PeripheryUARTKey => List(UARTParams(address = BigInt(0x64000000L)))
case PeripherySPIKey => List(SPIParams(rAddress = BigInt(0x64001000L)))
case PeripheryGPIOKey => List(GPIOParams(address = BigInt(0x64002000L), width=4))
})

class WithSystemModifications extends Config((site, here, up) => {
Expand Down Expand Up @@ -50,12 +52,16 @@ class WithVC707Tweaks extends Config (

new chipyard.harness.WithHarnessBinderClockFreqMHz(50) ++
new WithFPGAFrequency(50) ++ // default 50MHz freq

// harness binders
new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
new WithVC707UARTHarnessBinder ++
new WithVC707SPISDCardHarnessBinder ++
new WithVC707DDRMemHarnessBinder ++
new WithVC707GPIOHarnessBinder ++

// other configuration
new chipyard.iobinders.WithGPIOPunchthrough ++
new WithDefaultPeripherals ++
new chipyard.config.WithTLBackingMemory ++ // use TL backing memory
new WithSystemModifications ++ // setup busses, use sdboot bootrom, setup ext. mem. size
Expand Down
7 changes: 7 additions & 0 deletions fpga/src/main/scala/vc707/HarnessBinders.scala
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Expand Up @@ -37,3 +37,10 @@ class WithVC707DDRMemHarnessBinder extends HarnessBinder({
ddrClientBundle <> port.io
}
})


class WithVC707GPIOHarnessBinder extends HarnessBinder({
case (th: VC707FPGATestHarnessImp, port: GPIOPinsPort, chipId: Int) => {
th.vc707Outer.io_gpio_bb(port.gpioId).bundle <> port.io
}
})
13 changes: 12 additions & 1 deletion fpga/src/main/scala/vc707/TestHarness.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -9,14 +9,15 @@ import freechips.rocketchip.subsystem.{SystemBusKey}
import freechips.rocketchip.diplomacy.{IdRange, TransferSizes}
import freechips.rocketchip.prci._

import sifive.fpgashells.shell.xilinx.{VC707Shell, UARTVC707ShellPlacer, PCIeVC707ShellPlacer, ChipLinkVC707PlacedOverlay}
import sifive.fpgashells.shell.xilinx.{VC707Shell, UARTVC707ShellPlacer, PCIeVC707ShellPlacer, ChipLinkVC707PlacedOverlay, GPIOPeripheralVC707ShellPlacer}
import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly}
import sifive.fpgashells.shell._
import sifive.fpgashells.clocks.{PLLFactoryKey}
import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1.{XilinxVC707PCIeX1IO}

import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTPortIO}
import sifive.blocks.devices.spi.{PeripherySPIKey, SPIPortIO}
import sifive.blocks.devices.gpio.{PeripheryGPIOKey, GPIOPortIO}

import chipyard._
import chipyard.harness._
Expand Down Expand Up @@ -58,6 +59,16 @@ class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707She
/*** JTAG ***/
val jtagModule = dp(JTAGDebugOverlayKey).head.place(JTAGDebugDesignInput()).overlayOutput.jtag

/*** GPIO ***/
val gpio = Seq.tabulate(dp(PeripheryGPIOKey).size)(i => {
Overlay(GPIOOverlayKey, new GPIOPeripheralVC707ShellPlacer(this, GPIOShellInput()))
})

val io_gpio_bb = dp(PeripheryGPIOKey).map { p => BundleBridgeSource(() => (new GPIOPortIO(p))) }
(dp(GPIOOverlayKey) zip dp(PeripheryGPIOKey)).zipWithIndex.map { case ((placer, params), i) =>
placer.place(GPIODesignInput(params, io_gpio_bb(i)))
}

/*** UART ***/

// 1st UART goes to the VC707 dedicated UART
Expand Down