yosys
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A blinky project for the ULX3S v3.0.3 FPGA board
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Feb 16, 2019 - Verilog
Various IPs implemented in Verilog
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Feb 17, 2019 - SystemVerilog
Yosys passes to syntheize to NaN gates (à la http://tom7.org/nand/)
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Apr 26, 2019 - C++
XCrypto: a cryptographic ISE for RISC-V
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Jun 27, 2019 - Verilog
XCrypto: a cryptographic ISE for RISC-V
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Sep 4, 2019 - Verilog
VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes contro…
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Jul 21, 2020 - Coq
Z80 + USB + TinyFPGA-BX in Verilog using open-source Yosys+NextPNR
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Sep 8, 2020 - Verilog
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