Sol-1: A CPU/Computer System made from 74 series logic.
-
Updated
Jun 8, 2024 - C
Sol-1: A CPU/Computer System made from 74 series logic.
Verilator open-source SystemVerilog simulator and lint system
BDD Gherkin implementation in native SystemVerilog, based on UVM.
XLS: Accelerated HW Synthesis
Veryl: A Modern Hardware Description Language
Processador RISC-V multi ciclo com implementação RV32I construído em alguns dias de folga.
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
TX only RoCEv2. Super stripped down version of a RoCEv2 endpoint.
Single-Cycle CPU for Homework of Computer System Design in CUMT
Code generation tool for control and status registers
Basic counter example in verilog for Tang Nano 20k using Yosys, Nextpnr and openFPGALoader.
This is my first repo adding to my github account.
An HDL package manager.
Add a description, image, and links to the verilog topic page so that developers can more easily learn about it.
To associate your repository with the verilog topic, visit your repo's landing page and select "manage topics."