Research and Materials on Hardware implementation of Transformer Model
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Updated
Jun 8, 2024 - Jupyter Notebook
Research and Materials on Hardware implementation of Transformer Model
Productive and portable performance programming across spatial architectures (FPGAs, etc.) and vector architectures (GPUs, etc.)
Tiny ASIC implementation for "The Era of 1-bit LLMs All Large Language Models are in 1.58 Bits" matrix multiplication unit
Analytical modeling tool for CNNs running on array-based accelerators.
This project is focused on the design and verification of digital logic circuits, particularly targeting chip design using Verilog, SystemVerilog, and SVA. The main objectives included designing modules compliant with industry standards such as APB (Advanced Peripheral Bus), memory systems, and systolic matrix multiplication.
AI acceleration using matrix multiplication with half the multiplications
Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis
SystemVerilog module for matrix multiplication
AutoSA: Polyhedral-Based Systolic Array Compiler
SPICE and Behavioral simulation of systolic array equipped with error detection ABFT
In this repository you can find all of my projects for Parallel Processing Course when I was in 2nd semester of my master's at SUT.
Systolic Three Matrix Multiplier for Graph Convolutional Networks using High Level Synthesis
This is an unfinished test model of CNN, based on cnn.h5 Keras pretrained model EN10/KerasMNIST@4ef71d6/cnn.h5 .
A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
Template for project1 TPU
A general framework for optimizing DNN dataflow on systolic array
Systolic-array based Deep Learning Accelerator generator
EE599 Accelerated Computing on FPGA
A general framework for optimizing DNN dataflow on systolic array
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