rtl
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An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
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May 30, 2024 - Scala
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
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May 29, 2024 - Verilog
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
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May 29, 2024 - Verilog
Verilator open-source SystemVerilog simulator and lint system
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May 29, 2024 - C++
A flexible and scalable development platform for modern FPGA projects.
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May 29, 2024 - Python
Veryl: A Modern Hardware Description Language
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May 30, 2024 - Rust
🖥️ A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
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May 29, 2024 - VHDL
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
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May 28, 2024 - Python
Learning bluespec with bunch of tutorials and example codes
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May 28, 2024 - Bluespec
bus interface, integrating LFSR’s for streamlined register management. Enabled seamless master-peripheral communication, enhancing system efficiency. Orchestrated comprehensive design stages, yielding a versatile RTL architecture for diverse applications
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May 28, 2024 - Verilog
The computational speed of the dadda multiplier can be enhanced by partitioning the partial products. In process to achieve low power we have considered pass transistor for logical implementation.
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May 27, 2024 - Verilog
VeeR EL2 Core
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May 29, 2024 - SystemVerilog
The home of PHPFlasher, a PHP library for easy, customizable notification messages in web development projects. With implementations for Laravel, Symfony, and standalone use, PHPFlasher simplifies the process of adding notifications to web applications. The mono repository enables efficient collaboration and version control among developers.
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May 26, 2024 - PHP
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