CPU Design Based on RISCV ISA

It is a project on verilog which I had learned from a course taught by Prof. Indranil Sengupta at IIT Kharagpur.

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

high instruction-level-parallelism (ILP) using Resource-Flow-Execution

Projeto de leitura e processamento de dados de CSV em Node.js.

Chisel implementation of Neural Processing Unit for System on the Chip

CSC403: Computer Organization and Architecture [COA] & CSL403: Processor Architecture Lab [PAL] <Semester IV>

Implementation of Booth's algorithm for signed binary multiplication. It includes code designed for the PDUA processor, developed by the Pontificia Universidad Javeriana. The algorithm is provided in assembly language and includes its translation into executable binary instructions. Instructions are available in English and Spanish.

NanoGo a Go (golang) Subset for Homebrew / Hobby CPUs

Implementation of 3 stage pipelined processor based on RISC-V Instruction Set Architecture

This is a project currently doing under the module EN3021 Digital System Design, Semester 5, Department of Electronic & Telecommunication Engineering, University of Moratuwa, Sri Lanka.

Implementing a 32-bit processor using RISC-V architecture.

Welcome to the BitBlaster_10bit_Processor! Our custom-designed 10-bit processor, crafted meticulously as part of a project for a Digital Logic Design course at South Dakota State University.

2D RPG/RTS/Simulation game that lets you design a CPU & manage your corporation against other corporations.

CPR E 381 Project: Three MIPS Processor Designs - VHDL and Waveform Simulations

Pipelined MIPS Processor implementation, Computer Assignment for Computer Architecture course in Ferdowsi University of Mashhad

Computer Architecture Project Description

Laboratorio 1 de la materia de Arquitectura del Computador de la Licenciatura en Ciencias de la Computación de FAMAF (UNC)

Microcontroller implementation (VHDL) using an expanded version of the R8 ISA (PUCRS - Porto Alegre, Brasil), aiming FPGA synthesis

This repository contains the CENG3010 Computer Organization course projects. The first project involves developing a GUI-based 32-bit MIPS simulator, while the second project centers on designing a custom 16-bit MIPS-like processor with a unique instruction set.