integrated-circuits
Here are 108 public repositories matching this topic...
GDS3D is an application that can interpret so called IC layouts and render them in 3D. The program accepts standard GDSII files as input data. Along with the layout file, it requires a so called process definition file which contains the 3D parameters of the process being used. These files combined allow the program to create a 3D representation…
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Jun 12, 2024 - C++
HAL – The Hardware Analyzer
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Jun 13, 2024 - C++
My encounters with the magical world of LaserDisc...
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Jun 10, 2024 - Python
Hybrid IC design environment
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Jun 8, 2024 - Python
Devcontainers for Integrated-circuit design using the Viper IC design environment
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May 31, 2024 - Shell
Versatile tool to untangle wires. Made by chip researchers - for chip researchers. This means that the utility is wildly custom and incomprehensible.
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May 25, 2024 - C#
Parametric layout generator for digital, analog and mixed-signal integrated circuits
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May 23, 2024 - C
I made a digital counter on Proteus.
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May 17, 2024
Coding Projects for University Courses
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May 8, 2024 - Jupyter Notebook
The coolSAA1064 arduino library handles the 7 segment Philips / NXP SAA1064 driver for easily displaying and scrolling numbers and words on up to four displays.
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May 3, 2024 - C++
An UART Receiver that runs with a clock frequency of 125 MHz. The possible baudrates are 9600 bits per second and 115200 bits per second. It supports the parity bit. The received bytes are stored in a FIFO buffer with variable size.
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Apr 23, 2024 - SystemVerilog
4 stage pipeline implementation of a 16-bit RISC Processor in SystemVerilog that performs arithmetical, logical, data transfer, branch and halt operations.
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Apr 23, 2024 - SystemVerilog
3 stage pipeline implementation of a digital circuit that calculates DIT FFT in 8 points. It is made as an AXI-Lite Slave IP in AMD Vivado. It is successfully implemented in a block design that contains a Microblaze processor as the Master, an AXI Interconnect as the Bridge and the AXI-Lite FFT IP as Slave.
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Apr 13, 2024 - VHDL
FPU that does all the 4 fundamental arithmetic operations made as an AXI-Lite Slave IP in AMD Vivado. IEEE 754 was used. It can be successfully implemented on an Arty S7-50 FPGA board.
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Apr 13, 2024 - VHDL
Tool for plotting Ngspice simulation results with Pyplot.
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Mar 28, 2024 - Python
How to tell original from fake DS18B20 temperature sensors.
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Mar 19, 2024 - C++
广东工业大学自动化&集成学院本科课程学习笔记 Undergraduate course study notes of Schools of Automation and IC, GDUT
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Feb 26, 2024
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