FinFET Registers - Instituto de Informática da UFRGS

Multiplier is one of the most important arithmetic unit in Microprocessors and DSPs and also a major source of power dissipation. Reducing the power dissipation of multipliers is a key to satisfy the overall power budget of various digital circuits and systems. The project elaborates the steps required to design array multiplier. The fundamental…

Digital Electronic Circuits

Digital Electronic Circuits - Project 2

2-to-1 Decoder implemented using cmos, pseudo-nmos and dynamic logic

Latch and Flip Flop Analysis Using Hspice

UT VLSI CA1

Assignment of Microelectronic Circuits using HSPICE to simulate some of CMOS gates logics.

USC EE577A/577B related codes

An easy to use GUI for multi-objective optimization of electrical and electronic circuits using evolutionary and heuristic algorithms and HSPICE.

Python tools for generating and testing SPICE netlists/waveforms involving crossbar memory arrays in various configurations

Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format

We were required to design a "fully differential OpAmp" with some analysis, including open-loop gain ones and closed-loop ones in common-mode and differential-mode. Moreover, we simulated it with DC sweep, AC response, response with step, in order to obtain the waveform and check whether our design achieved the specification.

A center of gravity defuzzifier implemented as an analog CMOS circuit

HSPICE implementation of hybrid CMOS/Memristor BAM

Script that automates the process to create multiple Spice files through copying and appending. Each file is ran through subprocess and HSPICE, output is saved to find min Time Delay.

This place provide different SRAM cells netlist to be simulated with HSpice tool in sub-20nm FinFET technologies.

Multi-objective optimization based on sloping plate optimization algorithm called Multi-objective Inclined Planes system optimization algorithm (MOIPO) is presented in this link. The proposed method uses the concept of Pareto optimization to identify non-dominant positions and an external tank to maintain these positions.

This paper presents an intelligent sizing method to improve the performance and efficiency of a CMOS Ring Oscillator (RO). The proposed approach is based on the simultaneous utilization of powerful and new multi-objective optimization techniques along with a circuit simulator under a data link. The proposed optimizing tool creates a perfect trad…