asic-design

Here are 60 public repositories matching this topic...

chipsalliance / Cores-VeeR-EL2

VeeR EL2 Core

fpga processor riscv rtl risc-v open-source-hardware fusesoc verilator riscv32 western-digital axi4 ahb-lite asic-design el2

Updated May 31, 2024
SystemVerilog

dpretet / axi-crossbar

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Star

An AXI4 crossbar implementation in SystemVerilog

arm asic fpga processor riscv verilog soc fpga-soc interconnect amba crossbar riscv32 axi4 axi4-lite riscv64 monodraw axi4-protocol asic-design axi4-full

Updated May 28, 2024
SystemVerilog

shahed22 / Architectural-Design-for-Bus-interface-connected-with-LFSR

Star

bus interface, integrating LFSR’s for streamlined register management. Enabled seamless master-peripheral communication, enhancing system efficiency. Orchestrated comprehensive design stages, yielding a versatile RTL architecture for diverse applications

asic fsm interface architecture rtl verilog peripherals datapath soc testbench lfsr 32-bit 32bit bus-interface asic-design controlpath datapath-design lfsr-algorithm

Updated May 28, 2024
Verilog

shahed22 / Dadda-8-bit

Star

The computational speed of the dadda multiplier can be enhanced by partitioning the partial products. In process to achieve low power we have considered pass transistor for logical implementation.

fpga algorithms rtl verilog fulladder algorithms-implemented multiplier halfadder fpga-programming asic-design rtl-design multipliers

Updated May 27, 2024
Verilog

hughperkins / VeriGPU

Star

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

machine-learning gpu verification verilog gpu-acceleration hardware-designs risc-v asic-design risc-v-assembly

Updated May 25, 2024
SystemVerilog

abarajithan11 / deepsocflow

Star

An Open Workflow to Build Custom SoCs and run Deep Models at the Edge

asic ai fpga neural-network cnn dnn verilog systemverilog axi-stream asic-design hls4ml

Updated May 21, 2024
Python

Pritam-Sethuraman / ALU

Star

vhdl asic-verification asic-design

Updated May 19, 2024
VHDL

shrine-maiden-heavy-industries / torii-hdl

Star

A modern hardware definition language and toolchain based on Python

fpga hdl yosys digital-logic-design nextpnr asic-design torii-hdl

Updated May 18, 2024
Python

google / qkeras

Star

QKeras: a quantization deep learning library for Tensorflow Keras

machine-learning fpga deep-learning tensorflow accelerator keras quantization hardware-acceleration fpga-accelerator quantized-neural-networks asic-design quantized-networks

Updated May 3, 2024
Python

dpretet / async_fifo

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A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

asic fpga async verification verilog synthesis icarus-verilog fifo cdc hdl verilog-hdl fifo-queue fifo-cache verilator asic-design cross-clock-domain

Updated Apr 30, 2024
Verilog

AUCOHL / DFFRAM

Star

Standard Cell Library based Memory Compiler using FF/Latch cells

verilog vlsi vlsi-physical-design vlsi-circuits electronics-design asic-design

Updated Apr 29, 2024
Verilog

dpretet / friscv

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RISCV CPU implementation in SystemVerilog

asic fpga assembler riscv verilog systemverilog fpga-soc risc-v rv32i crossbar axi4 axi4-protocol asic-design riscv-cpu

Updated Apr 25, 2024
Coq

cpc / openasip

Star

Open Application-Specific Instruction Set processor tools (OpenASIP)

fpga hardware-designs asic-design hardware-accelerators

Updated Apr 24, 2024
C

williaml33moore / bathtub

Star

BDD Gherkin implementation in native SystemVerilog, based on UVM.

asic fpga bdd bdd-specs rtl verilog systemverilog uvm verilog-hdl bdd-framework asic-verification design-verification asic-design rtl-design soc-design soc-verification uvm-verification

Updated Jun 1, 2024
SystemVerilog

stnolting / neoTRNG

Star

🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).

cryptography asic fpga entropy random vhdl random-number-generators trng entropy-source ring-oscillator asic-design neorv32

Updated Apr 4, 2024
VHDL

arhamhashmi01 / rv32i-pipeline-processor

Star

This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog

vhdl verilog microprocessor hardware-designs computer-architecture gtkwave vlsi pipeline-processor risc-v rv32i verilator asic-design chip-design 5-stage-pipelined-processor rv32i-processor

Updated Mar 22, 2024
Verilog

abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU

Star

IC implementation of Systolic Array for TPU

asic fpga rtl verilog asic-verification asic-design

Updated Mar 4, 2024
Verilog

neeraj1397 / A-Primer-For-Physical-Design-Automation

Star

This repository contains python code snippets that implement several algorithms for automating the VLSI Physical Design process. This is based on the learnings from the course - EE5333W (Introduction to Physical Design Automation) at IITM.

algorithms eda python3 vlsi-physical-design vlsi-design asic-design vlsi-cad vlsi-pda