VeeR EH1 core
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Updated
May 29, 2023 - SystemVerilog
VeeR EH1 core
QKeras: a quantization deep learning library for Tensorflow Keras
OpenSource GPU, in Verilog, loosely based on RISC-V ISA
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
VeeR EL2 Core
Open Application-Specific Instruction Set processor tools (OpenASIP)
Standard Cell Library based Memory Compiler using FF/Latch cells
IC implementation of Systolic Array for TPU
Convolutional accelerator kernel, target ASIC & FPGA
🎲 A Tiny and Platform-Independent True Random Number Generator for any FPGA (and ASIC).
A place to keep my synthesizable verilog examples.
An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
Quasar 2.0: Chisel equivalent of SweRV-EL2
hardware design of universal NPU(CNN accelerator) for various convolution neural network
A modern hardware definition language and toolchain based on Python
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
RISCV CPU implementation in SystemVerilog
"Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"
Implementation of a binary search tree algorithm in a FPGA/ASIC IP
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