Assertion-Based Formal Verification of an AHB2APB bridge, featuring SystemVerilog assertions, RTL designs, and detailed documentation including a final report and project progression presentation.
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Updated
Mar 23, 2024 - SystemVerilog
Assertion-Based Formal Verification of an AHB2APB bridge, featuring SystemVerilog assertions, RTL designs, and detailed documentation including a final report and project progression presentation.
A reference book on System-on-Chip Design
This is a list of central processing units based on the ARM family of instruction sets designed by ARM Ltd. and third parties, sorted by version of the ARM instruction set, release and name. In 2005, ARM provided a summary of the numerous vendors who implement ARM cores in their design.
A textbook on understanding system on chip design
Verification IP for AMBA APB Protocol
A caravan equipped with API for creating bus protocols in Chisel with ease.
The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are converted into equivalent transfers on the APB.
Control and status register code generator toolchain
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