updated deca demistify target: direct plls, lfbuf burst 0x40

somhi · May 4, 2023 · e940bbd · e940bbd
1 parent 93e5607
commit e940bbd
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Showing 17 changed files with 1,398 additions and 70 deletions.
diff --git a/target/deca/common.yaml b/target/deca/common.yaml
@@ -5,6 +5,10 @@ here:
  - jtframe_mist_clocks.v
  - jtframe_mist.sv
  - jtframe_mist_base.v 
+ - pll6000/jtframe_pll6000.qip
+ - pll6144/jtframe_pll6144.qip
+ - pll6293/jtframe_pll6293.qip
+ - pll6671/jtframe_pll6671.qip
  # joystick direct support
  - jtframe_demistify_joy.v
  - mc2_hid_joy.vhd
@@ -35,10 +39,6 @@ target:
  # PLLs
  - pllgame/jtframe_pllgame.qip
  - pllgame96/jtframe_pllgame96.qip
- - pll6000/jtframe_pll6000.qip
- - pll6144/jtframe_pll6144.qip
- - pll6293/jtframe_pll6293.qip
- - pll6671/jtframe_pll6671.qip
  - from: mist
  unless: POCKET
  get:

diff --git a/target/deca/jtframe_lfbuf_ddr_deca.v b/target/deca/jtframe_lfbuf_ddr_deca.v
@@ -44,7 +44,7 @@ module jtframe_lfbuf_ddr_deca #(parameter
  output [DW-1:0] ln_pxl,
  output [VW-1:0] ln_v,
 
- //DDR3 DECA pinout TO BE MODIFIED
+ //DDR3
  output ddram_clk,
  input ddram_busy,
  output [7:0] ddram_burstcnt,
@@ -55,6 +55,7 @@ module jtframe_lfbuf_ddr_deca #(parameter
  output [63:0] ddram_din,
  output [7:0] ddram_be,
  output ddram_we,
+ output ddram_burstbegin,
 
  // Status
  input [7:0] st_addr,
@@ -89,7 +90,7 @@ jtframe_lfbuf_ddr_deca_ctrl #(.HW(HW),.VW(VW)) u_ctrl (
  .line ( line ),
  .scr_we ( scr_we ),
 
- //DDR3 DECA pinout TO BE MODIFIED
+ //DDR3
  .ddram_clk ( ddram_clk ),
  .ddram_busy ( ddram_busy ),
  .ddram_addr ( ddram_addr ),
@@ -100,6 +101,7 @@ jtframe_lfbuf_ddr_deca_ctrl #(.HW(HW),.VW(VW)) u_ctrl (
  .ddram_we ( ddram_we ),
  .ddram_burstcnt ( ddram_burstcnt ),
  .ddram_dout_ready( ddram_dout_ready ),
+ .ddram_burstbegin( ddram_burstbegin ),
 
  .st_addr ( st_addr ),
  .st_dout ( st_dout )

diff --git a/target/deca/jtframe_lfbuf_ddr_deca_ctrl.v b/target/deca/jtframe_lfbuf_ddr_deca_ctrl.v
@@ -44,7 +44,7 @@ module jtframe_lfbuf_ddr_deca_ctrl #(parameter
  output reg line,
  output reg scr_we,
 
- //DDR3 DECA pinout TO BE MODIFIED
+ //DDR3
  output ddram_clk,
  input ddram_busy,
  output [7:0] ddram_burstcnt,
@@ -55,6 +55,7 @@ module jtframe_lfbuf_ddr_deca_ctrl #(parameter
  output [63:0] ddram_din,
  output [7:0] ddram_be,
  output reg ddram_we,
+ output /*reg*/ ddram_burstbegin,
 
  // Status
  input [7:0] st_addr,
@@ -73,10 +74,11 @@ wire fb_over;
 
 assign fb_over = &fb_addr;
 assign ddram_clk = clk;
-assign ddram_burstcnt = 8'h80;
+assign ddram_burstcnt = 8'h40;
 assign ddram_addr = { 4'd3, {29-4-AW{1'd0}}, act_addr };
 assign ddram_din = { 48'd0, fb_din };
 assign ddram_be = 3;
+assign ddram_burstbegin = ddram_rd & ddram_we;
 assign nx_rd_addr = rd_addr + 1'd1;
 assign fb_dout = ddram_dout[15:0];
 
@@ -131,6 +133,7 @@ always @( posedge clk, posedge rst ) begin
  ln_done_l<= 0;
  do_wr <= 0;
  st <= IDLE;
+ //ddram_burstbegin <= 0;
  end else begin
  fb_done <= 0;
  ln_done_l <= ln_done;
@@ -148,36 +151,42 @@ always @( posedge clk, posedge rst ) begin
  ddram_we <= 0;
  ddram_rd <= 0;
  scr_we <= 0;
+ //ddram_burstbegin <= 0;
  if( lhbl_l & ~lhbl ) begin
  act_addr <= { ~frame, vrender, {HW{1'd0}} };
  ddram_rd <= 1;
  rd_addr <= 0;
  scr_we <= 1;
  st <= READ;
+ //ddram_burstbegin <= 1;
  end else if( do_wr && !fb_clr &&
  hcnt<hlim && lhbl ) begin // do not start too late so it doesn't run over H blanking
  fb_addr <= 0;
  act_addr <= { frame, ln_v, {HW{1'd0}} };
  ddram_we <= 1;
  do_wr <= 0;
  st <= WRITE;
+ //ddram_burstbegin <= 1;
  end
  end
  READ: if(!ddram_busy) begin
  ddram_rd <= 0;
+ //ddram_burstbegin <= 0;
  if( ddram_dout_ready ) begin
  rd_addr <= nx_rd_addr;
  if( &rd_addr ) begin
  st <= IDLE;
- end else if( &rd_addr[6:0] ) begin
+ end else if( &rd_addr[5:0] ) begin
  act_addr[HW-1:0] <= nx_rd_addr;
  ddram_rd <= 1;
+ //ddram_burstbegin <= 1;
  end
  end
  end
  WRITE: if(!ddram_busy) begin
- if( &fb_addr[6:0] ) begin
- act_addr[HW-1:7] <= act_addr[HW-1:7]+1'd1;
+ //ddram_burstbegin <= 0;
+ if( &fb_addr[5:0] ) begin
+ act_addr[HW-1:6] <= act_addr[HW-1:6]+1'd1;
  end
  fb_addr <= fb_addr +1'd1;
  if( fb_over ) begin

diff --git a/target/deca/jtframe_mist_clocks.v b/target/deca/jtframe_mist_clocks.v
@@ -59,6 +59,7 @@ assign pll_locked = pll0_lock & pll1_lock & pll2_lock;
 // TODO to be added pll 8 MHz for Turbo Chameleon 64 V1 
 // C10LP-RefKit has a 25Mhz and 12Mhz clock
 
+/*
 `ifdef DEMISTIFY_ATLAS_CYC // converts 12 to 27MHz
  pll_27 u_pllatlas( 
  .inclk0 ( clk_ext ),
@@ -84,10 +85,10 @@ assign pll_locked = pll0_lock & pll1_lock & pll2_lock;
  .outclk_0( clk27 ),
  .locked ( pll0_lock )
  );
-`else
+`else */
  assign clk27 = clk_ext;
  assign pll0_lock = 1;
-`endif
+// `endif
 
 `JTFRAME_PLL u_basepll(
  .inclk0 ( clk27 ),

diff --git a/target/deca/jtframe_mist_top.sv b/target/deca/jtframe_mist_top.sv
@@ -68,6 +68,21 @@ module mist_top(
  output VS_x,
  output VGA_DE,
  output VGA_CLK,
+
+ output ddram_clk,
+ input ddram_busy,
+ output [7:0] ddram_burstcnt,
+ output [31:3] ddram_addr,
+ input [63:0] ddram_dout,
+ input ddram_dout_ready,
+ output ddram_rd,
+ output [63:0] ddram_din,
+ output [7:0] ddram_be,
+ output ddram_we,
+ output ddram_burstbegin,
+
+ output clk_rom,
+ output rst,
  `endif 
 
  // user LED
@@ -94,7 +109,7 @@ module mist_top(
  localparam SDRAMW=22; // 32 MB
 `endif
 
-wire rst, rst_n, clk_sys, clk_rom, clk6, clk24, clk48, clk96;
+wire rst_n, clk_sys, clk6, clk24, clk48, clk96;
 wire [63:0] status;
 wire [31:0] joystick1, joystick2;
 wire [24:0] ioctl_addr;
@@ -498,66 +513,23 @@ assign dipsw = `ifdef JTFRAME_SIM_DIPS
  .ln_v ( ln_v ),
  .ln_we ( ln_we ),
 
-/* //DDR3 DECA pinout TO BE MODIFIED
- .ddram_clk ( DDRAM_CLK ),
- .ddram_busy ( DDRAM_BUSY ), //_i
- .ddram_addr ( DDRAM_ADDR ),
- .ddram_dout ( DDRAM_DOUT ), //_i
- .ddram_rd ( DDRAM_RD ), 
- .ddram_din ( DDRAM_DIN ),
- .ddram_be ( DDRAM_BE ),
- .ddram_we ( DDRAM_WE ),
- .ddram_burstcnt ( DDRAM_BURSTCNT ),
- .ddram_dout_ready( DDRAM_DOUT_READY ), //_i
- */
+ //DDR3 DECA pinout
+ .ddram_clk ( ddram_clk ),
+ .ddram_busy ( ddram_busy ), //_i
+ .ddram_addr ( ddram_addr ),
+ .ddram_dout ( ddram_dout ), //_i
+ .ddram_rd ( ddram_rd ), 
+ .ddram_din ( ddram_din ),
+ .ddram_be ( ddram_be ),
+ .ddram_we ( ddram_we ),
+ .ddram_burstcnt ( ddram_burstcnt ),
+ .ddram_dout_ready( ddram_dout_ready ), //_i
+ .ddram_burstbegin( ddram_burstbegin ),
+
  .st_addr ( st_addr ),
  .st_dout ( st_lpbuf )
  );
 
- /*
- ddr3 ddr3_dut (
- .pll_ref_clk (clk_rom ),
- .global_reset_n (~rst ),
- .soft_reset_n (~rst ),
- .afi_clk (afi_clk ),
- .afi_half_clk (afi_half_clk ),
- .afi_reset_n (afi_reset_n ),
- .afi_reset_export_n (afi_reset_export_n ),
- .mem_a (mem_a ),
- .mem_ba (mem_ba ),
- .mem_ck (mem_ck ),
- .mem_ck_n (mem_ck_n ),
- .mem_cke (mem_cke ),
- .mem_cs_n (mem_cs_n ),
- .mem_dm (mem_dm ),
- .mem_ras_n (mem_ras_n ),
- .mem_cas_n (mem_cas_n ),
- .mem_we_n (mem_we_n ),
- .mem_reset_n (mem_reset_n ),
- .mem_dq (mem_dq ),
- .mem_dqs (mem_dqs ),
- .mem_dqs_n (mem_dqs_n ),
- .mem_odt (mem_odt ),
- .avl_ready (avl_ready ),
- .avl_burstbegin (avl_burstbegin ),
- .avl_addr (avl_addr ),
- .avl_rdata_valid (avl_rdata_valid ),
- .avl_rdata (avl_rdata ),
- .avl_wdata (avl_wdata ),
- .avl_be (avl_be ),
- .avl_read_req (avl_read_req ),
- .avl_write_req (avl_write_req ),
- .avl_size (avl_size ),
- .local_init_done (local_init_done ),
- .local_cal_success (local_cal_success ),
- .local_cal_fail (local_cal_fail ),
- .pll_mem_clk (pll_mem_clk ),
- .pll_write_clk (pll_write_clk ),
- .pll_locked (pll_locked ),
- .pll_capture0_clk (pll_capture0_clk ),
- .pll_capture1_clk ( pll_capture1_clk)
- );
-*/
 
 `endif
 

diff --git a/target/deca/pll6000/jtframe_pll6000.ppf b/target/deca/pll6000/jtframe_pll6000.ppf
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone IV E" variation_name="jtframe_pll6000" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="areset" direction="input" scope="external" />
+<pin name="inclk0" direction="input" scope="external" source="clock" />
+<pin name="c0" direction="output" scope="external" source="clock" />
+<pin name="locked" direction="output" scope="external" />
+
+</global>
+</pinplan>
diff --git a/target/deca/pll6000/jtframe_pll6000.qip b/target/deca/pll6000/jtframe_pll6000.qip
@@ -0,0 +1,5 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "17.1"
+set_global_assignment -name IP_GENERATED_DEVICE_FAMILY "{Cyclone IV E}"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "jtframe_pll6000.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "jtframe_pll6000.ppf"]