merge PR #50

mem/acceptancetests/idealmemcontroller/test.go

@@ -52,8 +52,11 @@ func main() {
  agent.MaxAddress = *maxAddressFlag
  agent.WriteLeft = *numAccessFlag
  agent.ReadLeft = *numAccessFlag
- dram := idealmemcontroller.New("DRAM", engine, 4*mem.GB)
- dram.Latency = 100
+ dram := idealmemcontroller.MakeBuilder().
+ WithEngine(engine).
+ WithNewStorage(4 * mem.GB).
+ WithLatency(100).
+ Build("DRAM")
  agent.LowModule = dram.GetPortByName("Top")
 
  if *traceFileFlag != "" {

mem/acceptancetests/writearoundcache/test.go

@@ -91,7 +91,10 @@ func buildEnvironment() {
  tracing.CollectTrace(writeevictCache, tracer)
  }
 
- dram := idealmemcontroller.New("DRAM", engine, 4*mem.GB)
+ dram := idealmemcontroller.MakeBuilder().
+ WithEngine(engine).
+ WithNewStorage(4 * mem.GB).
+ Build("DRAM")
  lowModuleFinder.LowModule = dram.GetPortByName("Top")
 
  agent.LowModule = writeevictCache.GetPortByName("Top")

mem/acceptancetests/writebackcache/test.go

@@ -91,7 +91,10 @@ func buildEnvironment() {
  tracing.CollectTrace(writeBackCache, tracer)
  }
 
- dram := idealmemcontroller.New("DRAM", engine, 4*mem.GB)
+ dram := idealmemcontroller.MakeBuilder().
+ WithEngine(engine).
+ WithNewStorage(4 * mem.GB).
+ Build("DRAM")
  lowModuleFinder.LowModule = dram.GetPortByName("Top")
 
  agent.LowModule = writeBackCache.GetPortByName("Top")

mem/acceptancetests/writeevictcache/test.go

@@ -91,7 +91,10 @@ func buildEnvironment() {
  tracing.CollectTrace(writeevictCache, tracer)
  }
 
- dram := idealmemcontroller.New("DRAM", engine, 4*mem.GB)
+ dram := idealmemcontroller.MakeBuilder().
+ WithEngine(engine).
+ WithNewStorage(4 * mem.GB).
+ Build("DRAM")
  lowModuleFinder.LowModule = dram.GetPortByName("Top")
 
  agent.LowModule = writeevictCache.GetPortByName("Top")

mem/acceptancetests/writethroughcache/test.go

@@ -91,7 +91,10 @@ func buildEnvironment() {
  tracing.CollectTrace(writeevictCache, tracer)
  }
 
- dram := idealmemcontroller.New("DRAM", engine, 4*mem.GB)
+ dram := idealmemcontroller.MakeBuilder().
+ WithEngine(engine).
+ WithNewStorage(4 * mem.GB).
+ Build("DRAM")
  lowModuleFinder.LowModule = dram.GetPortByName("Top")
 
  agent.LowModule = writeevictCache.GetPortByName("Top")

mem/cache/writearound/cache_test.go

@@ -31,7 +31,10 @@ var _ = Describe("Cache", func() {
 
  engine = sim.NewSerialEngine()
  connection = directconnection.MakeBuilder().WithEngine(engine).WithFreq(1 * sim.GHz).Build("Conn")
- dram = idealmemcontroller.New("DRAM", engine, 4*mem.GB)
+ dram = idealmemcontroller.MakeBuilder().
+ WithEngine(engine).
+ WithNewStorage(4 * mem.GB).
+ Build("DRAM")
  lowModuleFinder = &mem.SingleLowModuleFinder{
  LowModule: dram.GetPortByName("Top"),
  }

mem/cache/writeback/writebackcache_test.go

@@ -66,9 +66,12 @@ var _ = Describe("Write-Back Cache Integration", func() {
  cacheModule.directory = directory
  cacheModule.storage = storage
 
- dram = idealmemcontroller.New("Dram", engine, 4*mem.GB)
- dram.Freq = 1 * sim.GHz
- dram.Latency = 200
+ dram = idealmemcontroller.MakeBuilder().
+ WithEngine(engine).
+ WithNewStorage(4 * mem.GB).
+ WithFreq(1 * sim.GHz).
+ WithLatency(200).
+ Build("DRAM")
 
  lowModuleFinder.LowModule = dram.GetPortByName("Top")
 

mem/cache/writeback/writebufferstage.go

@@ -251,7 +251,7 @@ func (wb *writeBufferStage) write() bool {
  // trans.accessReq().Meta().ID,
  // trans.evictingAddr, trans.evictingAddr,
  // trans.block.SetID, trans.block.WayID,
- // trans.evictingData,
+ // trans.evictingData,findInflightFetchByFetchReadReqID
  // )
 
  return true

mem/cache/writeevict/cache_test.go

@@ -30,7 +30,10 @@ var _ = Describe("Cache", func() {
 
  engine = sim.NewSerialEngine()
  connection = directconnection.MakeBuilder().WithEngine(engine).WithFreq(1 * sim.GHz).Build("Conn")
- dram = idealmemcontroller.New("DRAM", engine, 4*mem.GB)
+ dram = idealmemcontroller.MakeBuilder().
+ WithEngine(engine).
+ WithNewStorage(4 * mem.GB).
+ Build("DRAM")
  lowModuleFinder = &mem.SingleLowModuleFinder{
  LowModule: dram.GetPortByName("Top"),
  }

mem/cache/writethrough/cache_test.go

@@ -31,7 +31,10 @@ var _ = Describe("Cache", func() {
 
  engine = sim.NewSerialEngine()
  connection = directconnection.MakeBuilder().WithEngine(engine).WithFreq(1 * sim.GHz).Build("Conn")
- dram = idealmemcontroller.New("DRAM", engine, 4*mem.GB)
+ dram = idealmemcontroller.MakeBuilder().
+ WithEngine(engine).
+ WithNewStorage(4 * mem.GB).
+ Build("DRAM")
  lowModuleFinder = &mem.SingleLowModuleFinder{
  LowModule: dram.GetPortByName("Top"),
  }

mem/idealmemcontroller/builder.go

@@ -0,0 +1,109 @@
+package idealmemcontroller
+
+import (
+ "github.com/sarchlab/akita/v4/mem/mem"
+ "github.com/sarchlab/akita/v4/sim"
+)
+
+type Builder struct {
+ width int
+ latency int
+ freq sim.Freq
+ capacity uint64
+ engine sim.Engine
+ cacheLineSize int
+ topBufSize int
+ storage *mem.Storage
+ addressConverter mem.AddressConverter
+}
+
+// MakeBuilder returns a new Builder
+func MakeBuilder() Builder {
+ return Builder{
+ latency: 100,
+ freq: 1 * sim.GHz,
+ capacity: 4 * mem.GB,
+ cacheLineSize: 64,
+ width: 1,
+ topBufSize: 16,
+ }
+}
+
+// WithWidth sets the width of the memory controller
+func (b Builder) WithWidth(width int) Builder {
+ b.width = width
+ return b
+}
+
+// WithLatency sets the latency of the memory controller
+func (b Builder) WithLatency(latency int) Builder {
+ b.latency = latency
+ return b
+}
+
+// WithFreq sets the frequency of the memory controller
+func (b Builder) WithFreq(freq sim.Freq) Builder {
+ b.freq = freq
+ return b
+}
+
+// WithNewStorage sets the capacity of the memory controller
+func (b Builder) WithNewStorage(capacity uint64) Builder {
+ b.capacity = capacity
+ return b
+}
+
+// WithCacheLineSize sets the cache line size of the memory controller
+func (b Builder) WithCacheLineSize(cacheLineSize int) Builder {
+ b.cacheLineSize = cacheLineSize
+ return b
+}
+
+// WithEngine sets the engine of the memory controller
+func (b Builder) WithEngine(engine sim.Engine) Builder {
+ b.engine = engine
+ return b
+}
+
+// WithTopBufSize sets the size of the top buffer
+func (b Builder) WithTopBufSize(topBufSize int) Builder {
+ b.topBufSize = topBufSize
+ return b
+}
+
+// WithStorage sets the storage of the memory controller
+func (b Builder) WithStorage(storage *mem.Storage) Builder {
+ b.storage = storage
+ return b
+}
+
+// WithAddressConverter sets the address converter of the memory controller
+func (b Builder) WithAddressConverter(addressConverter mem.AddressConverter) Builder {
+ b.addressConverter = addressConverter
+ return b
+}
+
+// Build builds a new Comp
+func (b Builder) Build(
+ name string,
+) *Comp {
+ c := &Comp{
+ Latency: b.latency,
+ width: b.width,
+ }
+
+ c.TickingComponent = sim.NewTickingComponent(name, b.engine, b.freq, c)
+ c.Latency = b.latency
+ c.addressConverter = b.addressConverter
+
+ if b.storage == nil {
+ c.Storage = mem.NewStorage(b.capacity)
+ } else {
+ c.Storage = b.storage
+ }
+
+ c.topPort = sim.NewLimitNumMsgPort(c, b.topBufSize, name+".TopPort")
+ c.AddPort("Top", c.topPort)
+
+ return c
+}

mem/idealmemcontroller/idealmemcontroller.go → mem/idealmemcontroller/comp.go

@@ -13,7 +13,6 @@ import (
 
 type readRespondEvent struct {
  *sim.EventBase
-
  req *mem.ReadReq
 }
 
@@ -25,7 +24,6 @@ func newReadRespondEvent(time sim.VTimeInSec, handler sim.Handler,
 
 type writeRespondEvent struct {
  *sim.EventBase
-
  req *mem.WriteReq
 }
 
@@ -36,18 +34,17 @@ func newWriteRespondEvent(time sim.VTimeInSec, handler sim.Handler,
 }
 
 // An Comp is an ideal memory controller that can perform read and write
-//
 // Ideal memory controller always respond to the request in a fixed number of
 // cycles. There is no limitation on the concurrency of this unit.
 type Comp struct {
  *sim.TickingComponent
 
- topPort  sim.Port
- Storage  *mem.Storage
- Latency  int
- AddressConverter  mem.AddressConverter
- MaxNumTransaction int
- currNumTransaction int
+ topPort sim.Port
+ Storage *mem.Storage
+ Latency int
+ addressConverter mem.AddressConverter
+
+ width int
 }
 
 // Handle defines how the Comp handles event
@@ -68,17 +65,12 @@ func (c *Comp) Handle(e sim.Event) error {
 
 // Tick updates ideal memory controller state.
 func (c *Comp) Tick() bool {
- if c.currNumTransaction >= c.MaxNumTransaction {
- return false
- }
-
  msg := c.topPort.RetrieveIncoming()
  if msg == nil {
  return false
  }
 
  tracing.TraceReqReceive(msg, c)
- c.currNumTransaction++
 
  switch msg := msg.(type) {
  case *mem.ReadReq:
@@ -113,8 +105,8 @@ func (c *Comp) handleReadRespondEvent(e *readRespondEvent) error {
  req := e.req
 
  addr := req.Address
- if c.AddressConverter != nil {
- addr = c.AddressConverter.ConvertExternalToInternal(addr)
+ if c.addressConverter != nil {
+ addr = c.addressConverter.ConvertExternalToInternal(addr)
  }
 
  data, err := c.Storage.Read(addr, req.AccessByteSize)
@@ -130,14 +122,14 @@ func (c *Comp) handleReadRespondEvent(e *readRespondEvent) error {
  Build()
 
  networkErr := c.topPort.Send(rsp)
+
  if networkErr != nil {
  retry := newReadRespondEvent(c.Freq.NextTick(now), c, req)
  c.Engine.Schedule(retry)
  return nil
  }
 
  tracing.TraceReqComplete(req, c)
- c.currNumTransaction--
  c.TickLater()
 
  return nil
@@ -162,8 +154,8 @@ func (c *Comp) handleWriteRespondEvent(e *writeRespondEvent) error {
 
  addr := req.Address
 
- if c.AddressConverter != nil {
- addr = c.AddressConverter.ConvertExternalToInternal(addr)
+ if c.addressConverter != nil {
+ addr = c.addressConverter.ConvertExternalToInternal(addr)
  }
 
  if req.DirtyMask == nil {
@@ -188,7 +180,6 @@ func (c *Comp) handleWriteRespondEvent(e *writeRespondEvent) error {
  }
 
  tracing.TraceReqComplete(req, c)
- c.currNumTransaction--
  c.TickLater()
 
  return nil
@@ -197,23 +188,3 @@ func (c *Comp) handleWriteRespondEvent(e *writeRespondEvent) error {
 func (c *Comp) CurrentTime() sim.VTimeInSec {
  return c.Engine.CurrentTime()
 }
-
-// New creates a new ideal memory controller
-func New(
- name string,
- engine sim.Engine,
- capacity uint64,
-) *Comp {
- c := new(Comp)
-
- c.TickingComponent = sim.NewTickingComponent(name, engine, 1*sim.GHz, c)
- c.Latency = 100
- c.MaxNumTransaction = 8
-
- c.Storage = mem.NewStorage(capacity)
-
- c.topPort = sim.NewLimitNumMsgPort(c, 16, name+".TopPort")
- c.AddPort("Top", c.topPort)
-
- return c
-}