update idealmemcontroller

mem/idealmemcontroller/idealmemcontroller.go

@@ -67,12 +67,12 @@ func (c *Comp) Handle(e sim.Event) error {
 }
 
 // Tick updates ideal memory controller state.
-func (c *Comp) Tick(now sim.VTimeInSec) bool {
+func (c *Comp) Tick() bool {
  if c.currNumTransaction >= c.MaxNumTransaction {
  return false
  }
 
- msg := c.topPort.RetrieveIncoming(now)
+ msg := c.topPort.RetrieveIncoming()
  if msg == nil {
  return false
  }
@@ -82,10 +82,10 @@ func (c *Comp) Tick(now sim.VTimeInSec) bool {
 
  switch msg := msg.(type) {
  case *mem.ReadReq:
- c.handleReadReq(now, msg)
+ c.handleReadReq(msg)
  return true
  case *mem.WriteReq:
- c.handleWriteReq(now, msg)
+ c.handleWriteReq(msg)
  return true
  default:
  log.Panicf("cannot handle request of type %s", reflect.TypeOf(msg))
@@ -94,13 +94,15 @@ func (c *Comp) Tick(now sim.VTimeInSec) bool {
  return false
 }
 
-func (c *Comp) handleReadReq(now sim.VTimeInSec, req *mem.ReadReq) {
+func (c *Comp) handleReadReq(req *mem.ReadReq) {
+ now := c.CurrentTime()
  timeToSchedule := c.Freq.NCyclesLater(c.Latency, now)
  respondEvent := newReadRespondEvent(timeToSchedule, c, req)
  c.Engine.Schedule(respondEvent)
 }
 
-func (c *Comp) handleWriteReq(now sim.VTimeInSec, req *mem.WriteReq) {
+func (c *Comp) handleWriteReq(req *mem.WriteReq) {
+ now := c.CurrentTime()
  timeToSchedule := c.Freq.NCyclesLater(c.Latency, now)
  respondEvent := newWriteRespondEvent(timeToSchedule, c, req)
  c.Engine.Schedule(respondEvent)
@@ -121,7 +123,6 @@ func (c *Comp) handleReadRespondEvent(e *readRespondEvent) error {
  }
 
  rsp := mem.DataReadyRspBuilder{}.
- WithSendTime(now).
  WithSrc(c.topPort).
  WithDst(req.Src).
  WithRspTo(req.ID).
@@ -137,7 +138,7 @@ func (c *Comp) handleReadRespondEvent(e *readRespondEvent) error {
 
  tracing.TraceReqComplete(req, c)
  c.currNumTransaction--
- c.TickLater(now)
+ c.TickLater()
 
  return nil
 }
@@ -147,7 +148,6 @@ func (c *Comp) handleWriteRespondEvent(e *writeRespondEvent) error {
  req := e.req
 
  rsp := mem.WriteDoneRspBuilder{}.
- WithSendTime(now).
  WithSrc(c.topPort).
  WithDst(req.Src).
  WithRspTo(req.ID).
@@ -189,11 +189,15 @@ func (c *Comp) handleWriteRespondEvent(e *writeRespondEvent) error {
 
  tracing.TraceReqComplete(req, c)
  c.currNumTransaction--
- c.TickLater(now)
+ c.TickLater()
 
  return nil
 }
 
+func (c *Comp) CurrentTime() sim.VTimeInSec {
+ return c.Engine.CurrentTime()
+}
+
 // New creates a new ideal memory controller
 func New(
  name string,

mem/idealmemcontroller/idealmemcontroller_test.go

@@ -38,43 +38,43 @@ var _ = Describe("Ideal Memory Controller", func() {
  It("should stall if too many transactions are running", func() {
  memController.currNumTransaction = 8
 
- madeProgress := memController.Tick(10)
+ madeProgress := memController.Tick()
 
  Expect(madeProgress).To(BeFalse())
  })
 
  It("should process read request", func() {
  readReq := mem.ReadReqBuilder{}.
- WithSendTime(10).
  WithDst(memController.topPort).
  WithAddress(0).
  WithByteSize(4).
  Build()
- port.EXPECT().RetrieveIncoming(gomock.Any()).Return(readReq)
+ port.EXPECT().RetrieveIncoming().Return(readReq)
+ engine.EXPECT().CurrentTime().Return(sim.VTimeInSec(10))
 
  engine.EXPECT().
  Schedule(gomock.AssignableToTypeOf(&readRespondEvent{}))
 
- madeProgress := memController.Tick(10)
+ madeProgress := memController.Tick()
 
  Expect(madeProgress).To(BeTrue())
  Expect(memController.currNumTransaction).To(Equal(1))
  })
 
  It("should process write request", func() {
  writeReq := mem.WriteReqBuilder{}.
- WithSendTime(10).
  WithDst(memController.topPort).
  WithAddress(0).
  WithData([]byte{0, 1, 2, 3}).
  WithDirtyMask([]bool{false, false, true, false}).
  Build()
- port.EXPECT().RetrieveIncoming(gomock.Any()).Return(writeReq)
+ port.EXPECT().RetrieveIncoming().Return(writeReq)
+ engine.EXPECT().CurrentTime().Return(sim.VTimeInSec(10))
 
  engine.EXPECT().
  Schedule(gomock.AssignableToTypeOf(&writeRespondEvent{}))
 
- madeProgress := memController.Tick(10)
+ madeProgress := memController.Tick()
  Expect(madeProgress).To(BeTrue())
  Expect(memController.currNumTransaction).To(Equal(1))
  })
@@ -85,7 +85,6 @@ var _ = Describe("Ideal Memory Controller", func() {
  memController.currNumTransaction = 1
 
  readReq := mem.ReadReqBuilder{}.
- WithSendTime(10).
  WithDst(memController.topPort).
  WithAddress(0).
  WithByteSize(4).
@@ -95,6 +94,7 @@ var _ = Describe("Ideal Memory Controller", func() {
 
  engine.EXPECT().Schedule(gomock.Any())
  port.EXPECT().Send(gomock.AssignableToTypeOf(&mem.DataReadyRsp{}))
+ engine.EXPECT().CurrentTime().Return(sim.VTimeInSec(10))
 
  memController.Handle(event)
 
@@ -106,7 +106,6 @@ var _ = Describe("Ideal Memory Controller", func() {
  memController.Storage.Write(0, data)
 
  readReq := mem.ReadReqBuilder{}.
- WithSendTime(10).
  WithDst(memController.topPort).
  WithAddress(0).
  WithByteSize(4).
@@ -126,7 +125,6 @@ var _ = Describe("Ideal Memory Controller", func() {
  It("should handle write respond event without write mask", func() {
  data := []byte{1, 2, 3, 4}
  writeReq := mem.WriteReqBuilder{}.
- WithSendTime(10).
  WithDst(memController.topPort).
  WithAddress(0).
  WithData(data).
@@ -136,6 +134,7 @@ var _ = Describe("Ideal Memory Controller", func() {
 
  engine.EXPECT().Schedule(gomock.Any())
  port.EXPECT().Send(gomock.AssignableToTypeOf(&mem.WriteDoneRsp{}))
+ engine.EXPECT().CurrentTime().Return(sim.VTimeInSec(10))
 
  memController.Handle(event)
 
@@ -150,7 +149,6 @@ var _ = Describe("Ideal Memory Controller", func() {
  dirtyMask := []bool{false, true, false, false}
 
  writeReq := mem.WriteReqBuilder{}.
- WithSendTime(10).
  WithDst(memController.topPort).
  WithAddress(0).
  WithData(data).
@@ -160,6 +158,7 @@ var _ = Describe("Ideal Memory Controller", func() {
 
  engine.EXPECT().Schedule(gomock.Any())
  port.EXPECT().Send(gomock.AssignableToTypeOf(&mem.WriteDoneRsp{}))
+ engine.EXPECT().CurrentTime().Return(sim.VTimeInSec(10))
 
  memController.Handle(event)
  retData, _ := memController.Storage.Read(0, 4)
@@ -179,7 +178,6 @@ var _ = Describe("Ideal Memory Controller", func() {
  true, true, true, true, false, false, false, false,
  }
  writeReq := mem.WriteReqBuilder{}.
- WithSendTime(10).
  WithDst(memController.topPort).
  WithAddress(0).
  WithData(data).
@@ -203,7 +201,6 @@ var _ = Describe("Ideal Memory Controller", func() {
  data := []byte{1, 2, 3, 4}
 
  writeReq := mem.WriteReqBuilder{}.
- WithSendTime(10).
  WithDst(memController.topPort).
  WithAddress(0).
  WithData(data).