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Support "non-standard" interrupts and exceptions #211
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This PR is being prevented from merging because it presents one of the blocking labels: work in progress, do not merge. |
I think this is a good approach once it's clean and tested. I only had time to skim through it but don't see anything "wrong" with it. |
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Changes done. Please, take a look and let me know what you think. I personally think that we can improve it considerably. I will comment on the PR with my alternative idea.
Different approach: do not use generics nor enums at all in
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Thanks for the feedback @rmsyn ! I implemented my alternative approach in the |
That makes sense to me, too. Really either one can work, because the values are read from the
🤷 |
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I probably need more time to review the proc-macro stuff, but it looks good to me.
After an initial review, I do like the code organization in The unification of one |
So I think the new
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Currently, the
riscv
andriscv-rt
crates assume that the interrupt and exception sources are the ones gathered in the RISCV ISA. However, we do not support target-specific sources. Moreover, some RISC-V targets do not follow the standard interrupt scheme (e.g., ESP32 C3). Another example is the E310x microcontroller, which does not support supervisor interrupt sources.Proposal
Now that we have the
riscv-pac
trait to define interrupt and exception sources, we should be able to adapt the rest of the crates to rely on generic functions with constraints to these traits. For example, themcause
register can have something like this:By default,
I
andE
should be the standard enumerations (as we are doing now). Still, PACs will be able to opt out of this default implementation and provide their custom interrupt/exception enumeration.Next, we can enrich
riscv-rt
macros to automatically generate the necessary code for letting PACs inject their custom interrupt and exception tables. Also, in the case of vectored mode, we could generate the necessary vector table and so on.NOTE THAT THIS IS JUST MY PROPOSAL, but I would love to hear your opinion as well as clever mechanisms to implement this neatly.
I will do a self-review to point out some to-dos that I would like to discuss with you.
Solves #146