migration from KiCad 6 to 7

pcb/main/tGB-main.kicad_pro

@@ -1,5 +1,6 @@
 {
  "board": {
+ "3dviewports": [],
  "design_settings": {
  "defaults": {
  "board_outline_line_width": 0.049999999999999996,
@@ -63,20 +64,26 @@
  "rule_severities": {
  "annular_width": "error",
  "clearance": "error",
+ "connection_width": "warning",
  "copper_edge_clearance": "error",
+ "copper_sliver": "warning",
  "courtyards_overlap": "error",
  "diff_pair_gap_out_of_range": "error",
  "diff_pair_uncoupled_length_too_long": "error",
  "drill_out_of_range": "error",
  "duplicate_footprints": "warning",
  "extra_footprint": "warning",
+ "footprint": "error",
  "footprint_type_mismatch": "error",
  "hole_clearance": "error",
  "hole_near_hole": "error",
  "invalid_outline": "error",
+ "isolated_copper": "warning",
  "item_on_disabled_layer": "error",
  "items_not_allowed": "error",
  "length_out_of_range": "error",
+ "lib_footprint_issues": "ignore",
+ "lib_footprint_mismatch": "ignore",
  "malformed_courtyard": "error",
  "microvia_drill_out_of_range": "error",
  "missing_courtyard": "ignore",
@@ -86,9 +93,14 @@
  "padstack": "error",
  "pth_inside_courtyard": "ignore",
  "shorting_items": "error",
+ "silk_edge_clearance": "warning",
  "silk_over_copper": "warning",
  "silk_overlap": "warning",
  "skew_out_of_range": "error",
+ "solder_mask_bridge": "error",
+ "starved_thermal": "error",
+ "text_height": "warning",
+ "text_thickness": "warning",
  "through_hole_pad_without_hole": "error",
  "too_many_vias": "error",
  "track_dangling": "warning",
@@ -97,7 +109,6 @@
  "unconnected_items": "error",
  "unresolved_variable": "error",
  "via_dangling": "warning",
- "zone_has_empty_net": "error",
  "zones_intersect": "error"
  },
  "rule_severitieslegacy_courtyards_overlap": true,
@@ -107,18 +118,63 @@
  "allow_microvias": false,
  "max_error": 0.005,
  "min_clearance": 0.0,
+ "min_connection": 0.0,
  "min_copper_edge_clearance": 0.024999999999999998,
  "min_hole_clearance": 0.25,
  "min_hole_to_hole": 0.25,
  "min_microvia_diameter": 0.19999999999999998,
  "min_microvia_drill": 0.09999999999999999,
+ "min_resolved_spokes": 2,
  "min_silk_clearance": 0.0,
+ "min_text_height": 0.6,
+ "min_text_thickness": 0.08,
  "min_through_hole_diameter": 0.3,
  "min_track_width": 0.19999999999999998,
  "min_via_annular_width": 0.049999999999999996,
  "min_via_diameter": 0.39999999999999997,
+ "solder_mask_to_copper_clearance": 0.0,
  "use_height_for_length_calcs": true
  },
+ "teardrop_options": [
+ {
+ "td_allow_use_two_tracks": true,
+ "td_curve_segcount": 5,
+ "td_on_pad_in_zone": false,
+ "td_onpadsmd": true,
+ "td_onroundshapesonly": false,
+ "td_ontrackend": false,
+ "td_onviapad": true
+ }
+ ],
+ "teardrop_parameters": [
+ {
+ "td_curve_segcount": 0,
+ "td_height_ratio": 1.0,
+ "td_length_ratio": 0.5,
+ "td_maxheight": 2.0,
+ "td_maxlen": 1.0,
+ "td_target_name": "td_round_shape",
+ "td_width_to_size_filter_ratio": 0.9
+ },
+ {
+ "td_curve_segcount": 0,
+ "td_height_ratio": 1.0,
+ "td_length_ratio": 0.5,
+ "td_maxheight": 2.0,
+ "td_maxlen": 1.0,
+ "td_target_name": "td_rect_shape",
+ "td_width_to_size_filter_ratio": 0.9
+ },
+ {
+ "td_curve_segcount": 0,
+ "td_height_ratio": 1.0,
+ "td_length_ratio": 0.5,
+ "td_maxheight": 2.0,
+ "td_maxlen": 1.0,
+ "td_target_name": "td_track_end",
+ "td_width_to_size_filter_ratio": 0.9
+ }
+ ],
  "track_widths": [
  0.0,
  0.25,
@@ -133,7 +189,8 @@
  "zones_allow_external_fillets": false,
  "zones_use_no_outline": true
  },
- "layer_presets": []
+ "layer_presets": [],
+ "viewports": []
  },
  "boards": [],
  "cvpcb": {
@@ -317,18 +374,23 @@
  "rule_severities": {
  "bus_definition_conflict": "error",
  "bus_entry_needed": "error",
- "bus_label_syntax": "error",
  "bus_to_bus_conflict": "error",
  "bus_to_net_conflict": "error",
+ "conflicting_netclasses": "error",
  "different_unit_footprint": "error",
  "different_unit_net": "error",
  "duplicate_reference": "error",
  "duplicate_sheet_names": "error",
+ "endpoint_off_grid": "warning",
  "extra_units": "error",
  "global_label_dangling": "warning",
  "hier_label_mismatch": "error",
  "label_dangling": "error",
  "lib_symbol_issues": "warning",
+ "missing_bidi_pin": "warning",
+ "missing_input_pin": "warning",
+ "missing_power_pin": "error",
+ "missing_unit": "warning",
  "multiple_net_names": "warning",
  "net_not_bus_member": "warning",
  "no_connect_connected": "warning",
@@ -338,6 +400,7 @@
  "pin_to_pin": "error",
  "power_pin_not_driven": "error",
  "similar_labels": "warning",
+ "simulation_model_issue": "ignore",
  "unannotated": "error",
  "unit_value_mismatch": "error",
  "unresolved_variable": "error",
@@ -355,7 +418,7 @@
  "net_settings": {
  "classes": [
  {
- "bus_width": 12.0,
+ "bus_width": 12,
  "clearance": 0.2,
  "diff_pair_gap": 0.25,
  "diff_pair_via_gap": 0.25,
@@ -369,10 +432,10 @@
  "track_width": 0.25,
  "via_diameter": 0.8,
  "via_drill": 0.4,
- "wire_width": 6.0
+ "wire_width": 6
  },
  {
- "bus_width": 12.0,
+ "bus_width": 12,
  "clearance": 0.2,
  "diff_pair_gap": 0.25,
  "diff_pair_via_gap": 0.25,
@@ -381,30 +444,61 @@
  "microvia_diameter": 0.3,
  "microvia_drill": 0.1,
  "name": "Bold",
- "nets": [
- "+1V2",
- "+3V3",
- "+5V",
- "/1V2VO",
- "/3V3VO",
- "/VCC",
- "/VCC0",
- "/VCCPLL",
- "/VPP",
- "GND"
- ],
  "pcb_color": "rgba(0, 0, 0, 0.000)",
  "schematic_color": "rgba(0, 0, 0, 0.000)",
  "track_width": 0.5,
  "via_diameter": 0.8,
  "via_drill": 0.4,
- "wire_width": 6.0
+ "wire_width": 6
  }
  ],
  "meta": {
- "version": 2
+ "version": 3
  },
- "net_colors": null
+ "net_colors": null,
+ "netclass_assignments": null,
+ "netclass_patterns": [
+ {
+ "netclass": "Bold",
+ "pattern": "+1V2"
+ },
+ {
+ "netclass": "Bold",
+ "pattern": "+3V3"
+ },
+ {
+ "netclass": "Bold",
+ "pattern": "+5V"
+ },
+ {
+ "netclass": "Bold",
+ "pattern": "/1V2VO"
+ },
+ {
+ "netclass": "Bold",
+ "pattern": "/3V3VO"
+ },
+ {
+ "netclass": "Bold",
+ "pattern": "/VCC"
+ },
+ {
+ "netclass": "Bold",
+ "pattern": "/VCC0"
+ },
+ {
+ "netclass": "Bold",
+ "pattern": "/VCCPLL"
+ },
+ {
+ "netclass": "Bold",
+ "pattern": "/VPP"
+ },
+ {
+ "netclass": "Bold",
+ "pattern": "GND"
+ }
+ ]
  },
  "pcbnew": {
  "last_paths": {
@@ -420,6 +514,8 @@
  "schematic": {
  "annotate_start_num": 0,
  "drawing": {
+ "dashed_lines_dash_length_ratio": 12.0,
+ "dashed_lines_gap_length_ratio": 3.0,
  "default_line_thickness": 6.0,
  "default_text_size": 50.0,
  "field_names": [],
@@ -451,7 +547,11 @@
  "page_layout_descr_file": "",
  "plot_directory": "",
  "spice_adjust_passive_values": false,
+ "spice_current_sheet_as_root": false,
  "spice_external_command": "spice \"%I\"",
+ "spice_model_current_sheet_as_root": true,
+ "spice_save_all_currents": false,
+ "spice_save_all_voltages": false,
  "subpart_first_id": 65,
  "subpart_id_separator": 0
  },