GitHub - rishabhjain7b/UART: Complete UART project with specs(pdf), RTL and Testbench (Verilog)

rishabhjain7b / UART Public

Complete UART project with specs(pdf), RTL and Testbench (Verilog)

Name		Name	Last commit message	Last commit date
Latest commit History 15 Commits
work		work
BRG.v		BRG.v
BRG.v.bak		BRG.v.bak
BRG_tb.v		BRG_tb.v
BRG_tb.v.bak		BRG_tb.v.bak
PIPO.v		PIPO.v
PIPO.v.bak		PIPO.v.bak
PISO.v		PISO.v
PISO.v.bak		PISO.v.bak
SIPO.v		SIPO.v
SIPO.v.bak		SIPO.v.bak
UART.cr.mti		UART.cr.mti
UART.mpf		UART.mpf
UART.pdf		UART.pdf
counter_8bit.v		counter_8bit.v
counter_8bit.v.bak		counter_8bit.v.bak
counter_nbit.v		counter_nbit.v
counter_nbit.v.bak		counter_nbit.v.bak
dff.v		dff.v
dff.v.bak		dff.v.bak
mux8to1.v.bak		mux8to1.v.bak
sm_rx.v		sm_rx.v
sm_rx.v.bak		sm_rx.v.bak
sm_tx.v		sm_tx.v
sm_tx.v.bak		sm_tx.v.bak
uart.do		uart.do
uart_rx.v		uart_rx.v
uart_rx.v.bak		uart_rx.v.bak
uart_rx_tb.v		uart_rx_tb.v
uart_rx_tb.v.bak		uart_rx_tb.v.bak
uart_tb.v		uart_tb.v
uart_tb.v.bak		uart_tb.v.bak
uart_tx.v		uart_tx.v
uart_tx.v.bak		uart_tx.v.bak
uart_tx_tb.v		uart_tx_tb.v
uart_tx_tb.v.bak		uart_tx_tb.v.bak
vsim.wlf		vsim.wlf

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