OSCC IP Project contains a bundle of IPs which aim to improve development experience of processor and SoC design. Now it mainly focus on frontend and verification field. We hope it can be integrated by other components to build a common workflow for agile hardware development from frontend to backend one day.
IPs list and development state:
- SPC: SPEC complete
- RTF: RTL frozen
- SMT: SMOKE test
- UVV: UVM verif
- FUC: FUNCTION coverage
- COC: CODE coverage
- SOI: SoC integ
- FPE: FPGA emu
- TPT: TAPEOUT test
| IP | MILESTONE |
|---|---|
| archinfo |          |
| rng | |
| sram | |
| ps2 | |
| gpio | |
| clint | |
| pwm | |
| timer | |
| wdg | |
| rtc | |
| uart | |
| i2c | |
| spi | |
| vga | |
| plic | |
| rcu | |
| i2s |    |
| sdram | |
| psram | |
| tapeout1 |   |
- this PRIVATE repo contains some tapeout-verified IPs:
More Info
Refer to the template repo. If you want to create a new ip repo, You need to:
- Use this repository template to create a new repo
- Update the content
[IP NAME]inheaderfile and remove theheaderfile.
refer to the style.md.
If you want to contribute to this project, be sure to review the guidelines. This is an open project and contributions and collaborations are always welcome!! This project adheres to OSCC IP's code_of_conduct. By participating, you are expected to uphold this code.
we use GitHub issues for tracking requests and bugs, so please direct specific questions to issues panel.
The OSCC IP project strives to abide by generally accepted best practices in open-source software development, you can issue bugs, pull requests, new features and modification suggestions freely. Your feedbacks could help us ensure a bright future for this project. We value and treasure every issue or contribution, big or small. 😄
All of the IPs codes are redistributed or released under the OSI Approved LICENSE MulanPSL2.
