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A SPI master interface core for CPLD/FPGA

GPL-3.0 license

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Name		Name	Last commit message	Last commit date
Latest commit History 5 Commits
LICENSE		LICENSE
README.md		README.md
spi.v		spi.v
testbench.v		testbench.v

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SPI master core

(c)2018 Miguel Angel Rodriguez Jodar. See LICENSE for licensing details.

A SPI master interface core for CPLD/FPGA written in Verilog. Testbench, using a small SPI slave core, is included.