Make whitespace_013 silent on functional use of binary logic operators

[staerz]

Is your feature request related to a problem? Please describe.
VSG (3.13.1) currently reports an error on the following VHDL-2008 functional use of binary logic operators:

...
architecture tb of tester is
  signal eof : std_logic_vector(1 downto 0);
...
begin
...
  check_loop : process
  begin
      while nand(eof) loop
  ...

Describe the solution you'd like
As of VHDL-2008, binary operators such as nand, and etc. can be used as a function and return the "nand"-ed, "and"-ed etc. result of the passed signal.

whitespace_013 requires a space around the logical operators which usually isn't required for function calls.

The desired solution would be to make whitespace_013 recognise the functional use and then not kick in.
(from the view of the implementation: if the expression within the parenthesis contains a space then it's a parenthesis for logical hierarchy and whitespace_013 should be active, otherwise it's a functional use of the binary operator and whitespace_013 should not kick in)

Describe alternatives you've considered
The alternative is to not care or to add local exceptions everywhere ...

Additional context
VHDL-2008 is great!

[jeremiah-c-leary]

Good Evening @staerz ,

It has been awhile and I hope you are doing well.

I believe I found a case where I was not classifying the unary logical operator correctly in the following case:

  a<= b and and(some_signal);

So now the second and is properly classified and rule whitespace_013 does not activate.

When you get a chance could you check this out on your end?

Thanks,

--Jeremy

[jeremiah-c-leary]

Morning @staerz ,

Just wanted to ping you on this issue to see if you had time to check it out.

Thanks,

--Jeremy

[jeremiah-c-leary]

Evening @staerz ,

Just wanted to ping you on this to see if you had time to check out the implementation.

Happy New Year,

--Jeremy

[staerz]

Hey @jeremiah-c-leary,

I have some bad/sad news for you: I'm no longer dealing with VHDL as I left the project and the domain of firmware.
I will hence not be able to follow up on any of the issues that I have created.

You might ping @samdejong86 as he's still in the project and might take on this charge. If not, he might point you to another contact.

I thank you very much for all the effort that you put into VSG and wish you all best for its continuation as well as for you, personally!

Tschö, Steffen

[jeremiah-c-leary]

Morning @staerz ,

I have some bad/sad news for you: I'm no longer dealing with VHDL as I left the project and the domain of firmware.
I will hence not be able to follow up on any of the issues that I have created.

That is sad news for me.

I truly enjoyed our collaboration. Your rule and documentation suggestions have made a lasting impression on the project. I very much appreciate your contributions.

You might ping @samdejong86 as he's still in the project and might take on this charge. If not, he might point you to another contact.

Thank you for the contact. I will reach out.

I thank you very much for all the effort that you put into VSG and wish you all best for its continuation as well as for you, personally!

Thank you for the kind words. I wish you well in your next endeavor, and who knows, maybe our paths will cross again some day.

Best Regards,

--Jeremy