Booth's Multiplication Algorithm in VHDL

A multiplier module create in VHDL based in Booth's Algorithm to multiplication.

Inputs: Value A in 4 bits, Value B in 4 bits, Start, Reset, Clock pulse. Outputs: Produt of multiplication of A and B values in 8 bits.

Name		Name	Last commit message	Last commit date
Latest commit History 27 Commits
LICENSE		LICENSE
README.MD		README.MD
alu.vhd		alu.vhd
boothFSM.vhd		boothFSM.vhd
hdl-prj.json		hdl-prj.json
iter.vhd		iter.vhd
main.vhd		main.vhd
main_tb.vhd		main_tb.vhd
multiplex2.vhd		multiplex2.vhd
shift_reg.vhd		shift_reg.vhd
shift_reg_tb.vhd		shift_reg_tb.vhd

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