Skip to content
View emillal's full-sized avatar
πŸŒ†
πŸŒ†
Block or Report

Block or report emillal

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories

  1. RISC-V_based_MYTH_IIITB RISC-V_based_MYTH_IIITB Public

    RISC-V | TL-Verilog | Pipe-lining | Micro-Architecture | Makechip

    TL-Verilog 2

  2. PR_with_image_processing PR_with_image_processing Public

    Partial reconfiguration done for Image Processing | Image viewed through VGA | FPGA

    Verilog 2

  3. RTL_Workshop_VSD RTL_Workshop_VSD Public

    ASIC repository | Introduction to RTL

  4. Advanced_Physical_Design_using_OpenLANE-Sky130 Advanced_Physical_Design_using_OpenLANE-Sky130 Public

    Physical Design using Openlane

  5. System_design_with_FPGA System_design_with_FPGA Public

    Some Sample Verilog codes

    Verilog

  6. IIITB_auto_room_lc IIITB_auto_room_lc Public

    Physical Design of Automated room lighting | RISC-V

    Verilog