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Manual and Template Sources of Logic Circuit Laboratory (Verilog Templates)

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CE202-LC-Lab-Material

Logic Circuits Laboratory Manual and Code Templates

BSc, Amirkabir University of Technology (Tehran Polytechnic)

Course Supervisors (Instructors): Dr. M. Saheb Zamani and Dr. M. Sedighi

AUT Logic Circuits Laboratory Material and Template Sources

Assignments Quick Link

Manual Videos

Labs Description (Youtube)

Labs Description (Aparat)

How to complete Lab course as good student

[1] Clone repository to own account.

[2] Don't upload your codes in public domain.

[3] Update cloned branch for new assignments template

  • Add the remote, call it "upstream":
  • git remote add upstream https://github.com/aut-ce/CE202-LC-Lab-Manual
  • git fetch upstream
  • git checkout main
  • git rebase upstream/main

[4] Create new branch for assignments (git branch ca-lab-xx)

[5] commit your codes in branch (git add lab-xx & git commit)

[6] set branch remote to private repository like CEIT Gitlab (git push -u https://git.ce.aut.ac.ir/XYZ lab-xx)

[7] after passing the course, add your id and semester in last line of who-know-logic-lab.md file by pull request.

Teaching Assistants and Lab Instructors over Semesters

Dear Laboratory instructor, you can add your name and semester in who-had-logic-lab-ta.md file by pull request or create new issue.