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SnapperGPS/snappergps-pcb
SnapperGPS/snappergps-pcb PublicPrinted circuit board (PCB) design for snapshot GNSS receiver
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simple_superscalar_out-of-order_pipeline
simple_superscalar_out-of-order_pipeline PublicA superscalar and out-of-order instruction pipeline loosely based on the RISC-V ISA implemented in SystemVerilog.
SystemVerilog
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testbench_generator_for_SystemVerilog_modules
testbench_generator_for_SystemVerilog_modules PublicTakes a SystemVerilog module and creates a skeleton for a testbench. It parses the modport list and creates an instance in the testbench as well as some other useful stuff.
Python
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simple_logic_circuit_simulator
simple_logic_circuit_simulator PublicA simple console-based simulator for idealised logic circuits
C++
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cache_timing
cache_timing PublicIn this simple demo I show how one can indirectly access memory content by timing memory accesses
C++ 1
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