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👾 Design and implementation of a video decoder on an Altera Cyclone V FPGA board.

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FPGA Video Decoder

Design and implementation of a video decoder on an Altera Cyclone V FPGA board.

Design and Processing Elements

  • 3 Cores
  • 4 Mailboxes
  • 1 Read and write DMA
  • 1 2D IDCT HW accelerator
  • 1 Periodic timer

Methods and Tasks

  • Lossless decoding
  • Parallelizing the cores
  • HW accelerators
  • System level HW/SW co-design
  • FPGA resource utilization
  • Memory utilization
  • Inverse discrete cosine transform (IDCT)
  • Scheduling and synchronization
  • Cache coherency

License

MIT © Atakan Efe Kanman

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👾 Design and implementation of a video decoder on an Altera Cyclone V FPGA board.

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