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This contains all of my FPGA projects using Intel Quartus Prime IDE with microprocessor hardware during University including test benches. Will update when I track more down.

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Lab1: Light Activation on Microprocessor.vhd
Lab1: Light Activation on Microprocessor.vhd
 
 
Lab3: 2-bit counter.vhd
Lab3: 2-bit counter.vhd
 
 
Lab3: JK Flip-Flop Design.vhd
Lab3: JK Flip-Flop Design.vhd
 
 
Lab3: SM with JK-FF.vhd
Lab3: SM with JK-FF.vhd
 
 
Lab3: Test Bench for 2-bit Counter.vhd
Lab3: Test Bench for 2-bit Counter.vhd
 
 
Lab3: Test Bench for State Machine.vhd
Lab3: Test Bench for State Machine.vhd
 
 
Lab4: Complete Display.vhd
Lab4: Complete Display.vhd
 
 
Lab4: Hexidecimal Decoder.vhd
Lab4: Hexidecimal Decoder.vhd
 
 
Lab4: Second Half of Display.vhd
Lab4: Second Half of Display.vhd
 
 
Lab4: Sequential Sequence Detector Display.vhd
Lab4: Sequential Sequence Detector Display.vhd
 
 
Lab4: Seven_Segment_Decoder.vhd
Lab4: Seven_Segment_Decoder.vhd
 
 
Lab4: Test Bench for SSD.vhd
Lab4: Test Bench for SSD.vhd
 
 
Lab5: 3-Bit Counter.vhd
Lab5: 3-Bit Counter.vhd
 
 
Lab5: Integrating Light Shifting on Microprocessor.vhd
Lab5: Integrating Light Shifting on Microprocessor.vhd
 
 
Lab5: Test Bench.vhd
Lab5: Test Bench.vhd
 
 
Lab5: Universal Shift Register.vhd
Lab5: Universal Shift Register.vhd
 
 
Lab6: 26BitCounter.vhd
Lab6: 26BitCounter.vhd
 
 
Lab6: 4BitCounter.vhd
Lab6: 4BitCounter.vhd
 
 
Lab6: DigitalDecoder.vhd
Lab6: DigitalDecoder.vhd
 
 
Lab7: Logic Map for Static Error Correction.vhd
Lab7: Logic Map for Static Error Correction.vhd
 
 
Lab7: Test Bench for Static Error Demonstration.vht
Lab7: Test Bench for Static Error Demonstration.vht
 
 
Lab7: Test Bench for Static Error.vht
Lab7: Test Bench for Static Error.vht
 
 
Lab7_NAND.vhd
Lab7_NAND.vhd
 
 
Lab7_Static.vhd
Lab7_Static.vhd
 
 
README.md
README.md
 
 
seven_sdd_1.vht
seven_sdd_1.vht
 
 

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FPGA-Projects-

This contains all of my FPGA projects using Intel Quartus Prime IDE with microprocessor hardware during University including test benches. Currently Labs 1, 3 -> 7. 6 is currently incomplete however some of the counters and SSD used in previous projects were also used in 6.

Objectives:

1: Introduction to VHDL & the microprocessor unit 3: Using JK Flip Flops to implement a counter 4: Using '0' logic to display components for a Hexidecimal display 5: Using a Universal Shift Register & the microprocessor's LEDs to perform a "Night Rider" style light variant 6: Constructing a 24-hr digital clock which used several of the previously designed components including SSDs, Hexidecimal Decoders, & counters 7: Testing logic maps for static hazard and then correcting those errors. These used two seperate NAND gates to implement, the correcting variant involved a 10 ns delay. Special attention was brought to RTL testing as the logic maps for the correction code had to be adjusted or tinkered for proper function.

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This contains all of my FPGA projects using Intel Quartus Prime IDE with microprocessor hardware during University including test benches. Will update when I track more down.

Topics

counter fpga encoder decoder vhdl hexidecimal shiftregister flipflop staticerror

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