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sram_multiplexer_hw.tcl
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sram_multiplexer_hw.tcl
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# TCL File Generated by Component Editor 18.1
# Tue Jun 04 17:20:19 CST 2019
# DO NOT MODIFY
#
# sram_multiplexer "Lan Tian SRAM Multiplexer" v1.0
# 2019.06.04.17:20:19
#
#
#
# request TCL package from ACDS 16.1
#
package require -exact qsys 16.1
#
# module sram_multiplexer
#
set_module_property DESCRIPTION ""
set_module_property NAME sram_multiplexer
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME "Lan Tian SRAM Multiplexer"
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL SRAM_Multiplexer
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
add_fileset_file SRAM_Multiplexer.sv SYSTEM_VERILOG PATH comp/SRAM_Multiplexer.sv TOP_LEVEL_FILE
#
# parameters
#
#
# display items
#
#
# connection point clock
#
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""
add_interface_port clock CLK clk Input 1
#
# connection point reset
#
add_interface reset reset end
set_interface_property reset associatedClock clock
set_interface_property reset synchronousEdges DEASSERT
set_interface_property reset ENABLED true
set_interface_property reset EXPORT_OF ""
set_interface_property reset PORT_NAME_MAP ""
set_interface_property reset CMSIS_SVD_VARIABLES ""
set_interface_property reset SVD_ADDRESS_GROUP ""
add_interface_port reset RESET reset Input 1
#
# connection point avl
#
add_interface avl avalon end
set_interface_property avl addressUnits WORDS
set_interface_property avl associatedClock clock
set_interface_property avl associatedReset reset
set_interface_property avl bitsPerSymbol 8
set_interface_property avl burstOnBurstBoundariesOnly false
set_interface_property avl burstcountUnits WORDS
set_interface_property avl explicitAddressSpan 0
set_interface_property avl holdTime 0
set_interface_property avl linewrapBursts false
set_interface_property avl maximumPendingReadTransactions 0
set_interface_property avl maximumPendingWriteTransactions 0
set_interface_property avl readLatency 0
set_interface_property avl readWaitTime 1
set_interface_property avl setupTime 0
set_interface_property avl timingUnits Cycles
set_interface_property avl writeWaitTime 0
set_interface_property avl ENABLED true
set_interface_property avl EXPORT_OF ""
set_interface_property avl PORT_NAME_MAP ""
set_interface_property avl CMSIS_SVD_VARIABLES ""
set_interface_property avl SVD_ADDRESS_GROUP ""
add_interface_port avl AVL_READ read Input 1
add_interface_port avl AVL_WRITE write Input 1
add_interface_port avl AVL_WRITEDATA writedata Input 16
add_interface_port avl AVL_READDATA readdata Output 16
add_interface_port avl AVL_ADDR address Input 20
set_interface_assignment avl embeddedsw.configuration.isFlash 0
set_interface_assignment avl embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment avl embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment avl embeddedsw.configuration.isPrintableDevice 0
#
# connection point sram
#
add_interface sram conduit end
set_interface_property sram associatedClock clock
set_interface_property sram associatedReset ""
set_interface_property sram ENABLED true
set_interface_property sram EXPORT_OF ""
set_interface_property sram PORT_NAME_MAP ""
set_interface_property sram CMSIS_SVD_VARIABLES ""
set_interface_property sram SVD_ADDRESS_GROUP ""
add_interface_port sram SRAM_ADDR sram_addr Output 20
add_interface_port sram SRAM_CE_N sram_ce_n Output 1
add_interface_port sram SRAM_DQ sram_dq Bidir 16
add_interface_port sram SRAM_LB_N sram_lb_n Output 1
add_interface_port sram SRAM_OE_N sram_oe_n Output 1
add_interface_port sram SRAM_UB_N sram_ub_n Output 1
add_interface_port sram SRAM_WE_N sram_we_n Output 1
#
# connection point vga
#
add_interface vga conduit end
set_interface_property vga associatedClock clock
set_interface_property vga associatedReset ""
set_interface_property vga ENABLED true
set_interface_property vga EXPORT_OF ""
set_interface_property vga PORT_NAME_MAP ""
set_interface_property vga CMSIS_SVD_VARIABLES ""
set_interface_property vga SVD_ADDRESS_GROUP ""
add_interface_port vga VGA_DrawX vga_drawx Input 10
add_interface_port vga VGA_DrawY vga_drawy Input 10
add_interface_port vga VGA_VAL vga_val Output 16
#
# connection point clock2
#
add_interface clock2 clock end
set_interface_property clock2 clockRate 0
set_interface_property clock2 ENABLED true
set_interface_property clock2 EXPORT_OF ""
set_interface_property clock2 PORT_NAME_MAP ""
set_interface_property clock2 CMSIS_SVD_VARIABLES ""
set_interface_property clock2 SVD_ADDRESS_GROUP ""
add_interface_port clock2 CLK2 clk Input 1