This repository has been archived by the owner on Dec 5, 2020. It is now read-only.
-
Notifications
You must be signed in to change notification settings - Fork 2
/
lantian_mdio_hw.tcl
146 lines (122 loc) · 4.93 KB
/
lantian_mdio_hw.tcl
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
# TCL File Generated by Component Editor 18.1
# Wed May 08 22:12:59 CST 2019
# DO NOT MODIFY
#
# lantian_mdio "Lan Tian Ethernet MDIO Clause 22" v1.0
# 2019.05.08.22:12:59
#
#
#
# request TCL package from ACDS 16.1
#
package require -exact qsys 16.1
#
# module lantian_mdio
#
set_module_property DESCRIPTION ""
set_module_property NAME lantian_mdio
set_module_property VERSION 1.0
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property AUTHOR ""
set_module_property DISPLAY_NAME "Lan Tian Ethernet MDIO Clause 22"
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" ""
set_fileset_property QUARTUS_SYNTH TOP_LEVEL lantian_mdio
set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE true
add_fileset_file lantian_mdio.sv SYSTEM_VERILOG PATH comp/lantian_mdio/lantian_mdio.sv TOP_LEVEL_FILE
#
# parameters
#
add_parameter CLOCK_DIVIDER STD_LOGIC_VECTOR 40
set_parameter_property CLOCK_DIVIDER DEFAULT_VALUE 40
set_parameter_property CLOCK_DIVIDER DISPLAY_NAME CLOCK_DIVIDER
set_parameter_property CLOCK_DIVIDER TYPE STD_LOGIC_VECTOR
set_parameter_property CLOCK_DIVIDER UNITS None
set_parameter_property CLOCK_DIVIDER ALLOWED_RANGES 0:255
set_parameter_property CLOCK_DIVIDER HDL_PARAMETER true
#
# display items
#
#
# connection point avalon_slave
#
add_interface avalon_slave avalon end
set_interface_property avalon_slave addressUnits WORDS
set_interface_property avalon_slave associatedClock clock
set_interface_property avalon_slave associatedReset reset
set_interface_property avalon_slave bitsPerSymbol 8
set_interface_property avalon_slave burstOnBurstBoundariesOnly false
set_interface_property avalon_slave burstcountUnits WORDS
set_interface_property avalon_slave explicitAddressSpan 0
set_interface_property avalon_slave holdTime 0
set_interface_property avalon_slave linewrapBursts false
set_interface_property avalon_slave maximumPendingReadTransactions 0
set_interface_property avalon_slave maximumPendingWriteTransactions 0
set_interface_property avalon_slave readLatency 0
set_interface_property avalon_slave readWaitTime 1
set_interface_property avalon_slave setupTime 0
set_interface_property avalon_slave timingUnits Cycles
set_interface_property avalon_slave writeWaitTime 0
set_interface_property avalon_slave ENABLED true
set_interface_property avalon_slave EXPORT_OF ""
set_interface_property avalon_slave PORT_NAME_MAP ""
set_interface_property avalon_slave CMSIS_SVD_VARIABLES ""
set_interface_property avalon_slave SVD_ADDRESS_GROUP ""
add_interface_port avalon_slave avalon_slave_address address Input 5
add_interface_port avalon_slave avalon_slave_read read Input 1
add_interface_port avalon_slave avalon_slave_readdata readdata Output 32
add_interface_port avalon_slave avalon_slave_waitrequest waitrequest Output 1
add_interface_port avalon_slave avalon_slave_write write Input 1
add_interface_port avalon_slave avalon_slave_writedata writedata Input 32
set_interface_assignment avalon_slave embeddedsw.configuration.isFlash 0
set_interface_assignment avalon_slave embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment avalon_slave embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment avalon_slave embeddedsw.configuration.isPrintableDevice 0
#
# connection point clock
#
add_interface clock clock end
set_interface_property clock clockRate 0
set_interface_property clock ENABLED true
set_interface_property clock EXPORT_OF ""
set_interface_property clock PORT_NAME_MAP ""
set_interface_property clock CMSIS_SVD_VARIABLES ""
set_interface_property clock SVD_ADDRESS_GROUP ""
add_interface_port clock clk clk Input 1
#
# connection point reset
#
add_interface reset reset end
set_interface_property reset associatedClock clock
set_interface_property reset synchronousEdges DEASSERT
set_interface_property reset ENABLED true
set_interface_property reset EXPORT_OF ""
set_interface_property reset PORT_NAME_MAP ""
set_interface_property reset CMSIS_SVD_VARIABLES ""
set_interface_property reset SVD_ADDRESS_GROUP ""
add_interface_port reset reset reset Input 1
#
# connection point mdio
#
add_interface mdio conduit end
set_interface_property mdio associatedClock clock
set_interface_property mdio associatedReset ""
set_interface_property mdio ENABLED true
set_interface_property mdio EXPORT_OF ""
set_interface_property mdio PORT_NAME_MAP ""
set_interface_property mdio CMSIS_SVD_VARIABLES ""
set_interface_property mdio SVD_ADDRESS_GROUP ""
add_interface_port mdio mdc mdc Output 1
add_interface_port mdio mdio_in mdio_in Input 1
add_interface_port mdio mdio_out mdio_out Output 1
add_interface_port mdio mdio_oen mdio_oen Output 1
add_interface_port mdio phy_addr phy_addr Input 5