Faster build for only changed module #1834
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Hey there, excuse my novice, but I am working on MMIO accelerator for chipyard and I keep changing the chisel implementation of the module (as a chisel submodule generator) but no changes to the interface in regmap. I am not planning currently on tape out, but only rte simulation, is there a way to make the make in sims/verilator only build the generator instead of the whole SoC? it takes too long time for me every time I make any small change! Thank you for your help |
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No, any RTL change requires a complete rerun of both chisel elaboration, verilation, and compilation of the RTL simulator. If you have access, you can try using VCS, which offers a much faster compilation flow. You can also pass |
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No, any RTL change requires a complete rerun of both chisel elaboration, verilation, and compilation of the RTL simulator.
If you have access, you can try using VCS, which offers a much faster compilation flow.
You can also pass
-jflags to make to parallelize the compilation process.