/
ousia.core
63 lines (60 loc) · 1.45 KB
/
ousia.core
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CAPI=2:
name: ::ousia:0
generate:
wb_intercon:
generator: wb_intercon_gen
parameters:
masters:
ibus:
slaves: [ram]
dbus:
slaves: [ram, uart, gpio]
slaves:
ram:
offset: 0x80000000
size: 0x7fffffff
uart:
offset: 0x10000000
size: 0x10000000
gpio:
offset: 0x20000000
size: 0x10000000
filesets:
naive_soc:
files:
- Naive.v
- naive_soc.v
file_type: verilogSource
depend: [wb_intercon, uart16550, gpio]
cocotb:
files:
- tb/cocotb_top.v
file_type: verilogSource
cyc10:
files:
- board/step-cyc10/pin.tcl: { file_type: tclSource }
- board/step-cyc10/timing.sdc: { file_type: SDC }
- board/step-cyc10/pll.qip: { file_type: QIP }
- board/step-cyc10/pll.v: { file_type: verilogSource }
- board/step-cyc10/ram.qip: { file_type: QIP }
- board/step-cyc10/ram.v: { file_type: verilogSource }
- board/step-cyc10/cyc10_top.v: { file_type: verilogSource }
targets:
default:
filesets: [naive_soc, cocotb]
generate: [wb_intercon]
toplevel: cocotb_top
default_tool: verilator
tools:
verilator:
mode: lint-only
cyc10:
filesets: [naive_soc, cyc10]
generate: [wb_intercon]
toplevel: cyc10_top
default_tool: quartus
tools:
quartus:
family: Cyclone 10 LP
device: 10CL016YU256C8G
# vim:ft=yaml