Add a "get mask" instruction for vector registers

[mbitsnbites]

Add an instruction that queries the "mask state" of vector registers. The instruction should take one or two vector registers as source operands and a scalar register as the destination operand. For each register, the mask state can be one of:

1. All bits in all elements are cleared.
2. All bits in all elements are set.
3. At least one bit is set and at least one bit is cleared.

The mask state will be returned as a 32-bit value as follows:

• All bits cleared: 0x00000000 (zero)
• All bits set: 0xFFFFFFFF (-1)
• Mixed set/cleared: 0x00000001 (+1)

That way it's natural to use the same classes of branch instructions that you would use for packed operations, for instance.

When using two different registers as source operands, the resulting state will be the combination of the two states, as if the two registers were concatenated (e.g. 0x00000000 will only be returned if both registers have all bits cleared).

In hardware the instruction can either be implemented as an ALU operation that checks the content of all vector elements, or as a state in the register file that is updated at each write to the vector register file (the latter requires slightly more hardware, but would save CPU cycles).

In a future extension, the state could be possible to query directly with branch instructions (using a vector register as the branch condition). Since it's slightly more complex to implement in hardware, let's not mandate it yet.

Another possible extension would be to allow the source operands to be both vectors and scalars, though the value would probably be limited (essentially it only provides a convenient way to convert "the registers contain mixed bits" to "+1").

[mbitsnbites]

Open question: should the mask state be based on the current VL (good fit for an ALU implementation), or the register length (good fit for a register state implementation)?