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This repository has been archived by the owner on Sep 2, 2023. It is now read-only.
Immediate mode rotation is currently possible to do with two instructions: EBFU + IBF.
; Rotate R1 right 7 positions (result in R2).
ebfu r2, r1, #<7:25>
ibf r2, r1, #<25:7>
Variable (register based) rotation on the other hand is much trickier and requires about five instructions, e.g:
; Rotate R1 right the number of positions specified by R2 (result in R1).
and r2, r2, #31
lsr r3, r1, r2
sub r2, #32, r2
lsl r1, r1, r2
or r1, r1, r3
Bit rotate is common in crypto, and it would be very helpful to have dedicated rotate instructions.
Suggestion
Consider adding:
ROL ra, rb, rc
ROR ra, rb, rc
ROR ra, rb, #imm
Note: We only need one immediate variant since left rotate can easily be expressed as a right rotate when the constant shift amount is known. Possibly we can do without an immediate mode ROR (investigate).
Questions
Encoding of immediate mode ROR?
Using a format C slot wastes lots of encoding space, since we only need 5 of the 15 immediate bits. Can we live without the immediate mode rotate (require an extra LDI), or should we introduce a new encoding?
We could, for instance, use a variant of format A where the 5-bit register specifier is interpreted as an immediate value. This would, however, be a poor fit for MRISC64.
Hardware implications?
How well would the rotate functionality match the MKBF/EBF/IBF hardware? Would we introduce more gate delay?
The text was updated successfully, but these errors were encountered:
Problem
Immediate mode rotation is currently possible to do with two instructions:
EBFU
+IBF
.Variable (register based) rotation on the other hand is much trickier and requires about five instructions, e.g:
Bit rotate is common in crypto, and it would be very helpful to have dedicated rotate instructions.
Suggestion
Consider adding:
Note: We only need one immediate variant since left rotate can easily be expressed as a right rotate when the constant shift amount is known. Possibly we can do without an immediate mode ROR (investigate).
Questions
Encoding of immediate mode ROR?
Using a format C slot wastes lots of encoding space, since we only need 5 of the 15 immediate bits. Can we live without the immediate mode rotate (require an extra
LDI
), or should we introduce a new encoding?We could, for instance, use a variant of format A where the 5-bit register specifier is interpreted as an immediate value. This would, however, be a poor fit for MRISC64.
Hardware implications?
How well would the rotate functionality match the MKBF/EBF/IBF hardware? Would we introduce more gate delay?
The text was updated successfully, but these errors were encountered: