{"payload":{"header_redesign_enabled":false,"results":[{"id":"153564416","archived":false,"color":"#b2b7f8","followers":29,"has_funding_file":false,"hl_name":"matt-alencar/fpga-uart-tx-rx","hl_trunc_description":"Basic UART TX/RX module for FPGA","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":153564416,"name":"fpga-uart-tx-rx","owner_id":44207758,"owner_login":"matt-alencar","updated_at":"2018-10-18T05:09:13.437Z","has_issues":true}},"sponsorable":false,"topics":["fpga","verilog","uart","hdl","uart-protocol","soft-core","uart-interface"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":76,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253Amatt-alencar%252Ffpga-uart-tx-rx%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/matt-alencar/fpga-uart-tx-rx/star":{"post":"JwW-HoDIwGU5m6IZiYMU3Hn809DxPG2RulrN0cZgnmbiwjfgnAwAiHCGErxpEXkFrf3MW_GPbXN1dprYC7Zfwg"},"/matt-alencar/fpga-uart-tx-rx/unstar":{"post":"qg4Hpbh5xXc1IPzAeTk1tBdYo23b-S7N53vg8m6roivFhHDWf6reh8Ppsa44r8C6j4GFh36wjeJQiFoxb74Mtw"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"ykCO99N7STkRFDlg0kiPZTGEafiR2ARN1vRo_gNN2X8v3SuYAoZptLwGrcEG7YF7F7NEiyMHT6FbofF7Pl4jlw"}}},"title":"Repository search results"}