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Generating complete schematic out of VHDL files #7
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You may be looking to use something like netlistsvg. I wrote a blog post on how to generate blog diagrams from VHDL using the open source FPGA toolchain here. |
If you are using Sphinx, you might also want to consider https://sphinxcontrib-hdl-diagrams.readthedocs.io/en/latest/ |
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Feb 6, 2023
Make symbolator_sphinx work with newer sphinx verions
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Hello, do you think one day symbolator could be used to parse one or more VHDL files to generate a schematic of the instanced components/wires?
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