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Verilog unpacked arrays not supported #6
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ghost
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Verilog arrays not supported
Verilog unpacked arrays not supported
Aug 22, 2018
zebreus
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Jun 9, 2023
Changed all the uses of .format to f-strings instead. Signed-off-by: Wouter van Verre <[email protected]>
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Hi Kevin,
I have this module
module abc (
input clk;
input rst;
input [7:0] data[4];
output [7:0]
);
// Missing code doesn't change symbolator behaviour
endmodule
Symbolator generates this:
So there seems to be a problem with unpacked arrays.
Best wishes and keep on rockin'!
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