65% - 94% mba cos value generates the same result 90%

[congxu2016]

I am using pqos library (i.e. pqos_mba_set()) to set the MBA COS dynamically. I found no matter what value I use between 65% - 94% on my machine, the MBA COS is ultimately set to 90%. My skylake platform is Xeon Gold 6150. OS is ubuntu 16.04.2 (kernel 4.13).

[mdcornu]

Thanks for contacting us with this issue.
We will investigate and report back when we have updates.

Regards,
Marcel

[meteorfox]

I also noticed this, I tried writing the MSR directly using wrmsr and noticed it still returned "0xA" which corresponds to 100 - 0xA or 90% of available bandwidth.

MBA MSR starts at address 0xD50

To set COS1, that would be address 0xD50+1 => 0xD51.

In my case, I tried to set it to 70% available bandwidth, that's translates to 30% throttle or 0x1E.

# rdmsr 0xD51
0

# wrmsr 0xD51 0x1E

# rdmsr 0xD51
a    <== Should be 0x1e not 0xa

[gureya]

Hi,

Has this issue been resolved, I'm also getting a similar behavior on Intel(R) Xeon(R) Silver 4114 i.e., the MBA levels of 70% & 80% are ultimately set to 90%

[madhura-a]

Similar behavior is observed on Intel(R) Xeon(R) Gold 6126 CPU. Not only for MBA levels, for some values of LLC cache ways values are not set properly. For example, When I try to set LLC cache ways to 0x400, it is updating to 0x600.

[limitedge]

These issues are under investigation, thanks for your patience.

[limitedge]

This is a known issue on certain generations of Xeon eg Skylake and Cascadelake which should now be in the sightings report, and this will be fixed in subsequent generations. Thanks