bitstream tutorial model build error

[ImNotACoder]

Hi all,

I'm currently facing this issue even after installing the required IP for the pynq-z2 FPGA, which is the exact setup detailed by the tutorial. My vivado version, 2020.1, is also capable of detecting the board files.

Here is a snippet from the jupyter notebook tutorial 7a on bitstream. I have left everything else untouched less changing the fpga part.
Particularly, the error stems from this code in the tutorial hls_model.build(csim=False, export=True, bitfile=True).

` Slave segment '/processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM' is being assigned into address space '/axi_dma_0/Data_S2MM' at <0x0000_0000 [ 512M ]>.
# startgroup
# create_bd_cell -type ip -vlnv xilinx.com:hls:${project_name}_axi:1.0 ${project_name}_axi_0
ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors.

    while executing
"create_bd_cell -type ip -vlnv xilinx.com:hls:${project_name}_axi:1.0 ${project_name}_axi_0"
    (file "design.tcl" line 39)
INFO: [Common 17-17] undo 'startgroup'
INFO: [Common 17-206] Exiting Vivado at Tue Jul  4 11:26:48 2023...

ERROR: [BD 5-390] IP definition not found for VLNV: xilinx.com:hls:myproject_axi:1.0 

Vivado synthesis report not found.
Cosim report not found.
Timing report not found. 

`

I'm relatively new to Vivado and the FPGA build process, although I suspect its something to do with where i source the files. Do let me know if there are files I can provide to aid your assistance!

[obsidian-1]

I had the same issue,
Vivado 2019.2
The error has something to do with the current date being larger than a type used to store the date in the tcl scipt provided by hls4ml.
changed my device date to 2019 and it worked perfectly